Including gate level verilogs
Now that each is its own hard ip, they need to be included
Showing
- verilog/includes/includes.gl+sdf.caravel_user_project 5 additions, 0 deletionsverilog/includes/includes.gl+sdf.caravel_user_project
- verilog/includes/includes.gl.caravel_user_project 5 additions, 0 deletionsverilog/includes/includes.gl.caravel_user_project
- verilog/includes/includes.rtl.caravel_user_project 3 additions, 0 deletionsverilog/includes/includes.rtl.caravel_user_project
Loading
Please register or sign in to comment