Adding separat hard cores for each FSM
OpenROAD is kind of brain damaged and optimizes away my SRAM otherwise.
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- openlane/AI_Accelerator_Top/config.json 12 additions, 3 deletionsopenlane/AI_Accelerator_Top/config.json
- openlane/Control_Unit/base_user_proj.sdc 3 additions, 0 deletionsopenlane/Control_Unit/base_user_proj.sdc
- openlane/Control_Unit/config.json 60 additions, 0 deletionsopenlane/Control_Unit/config.json
- openlane/Control_Unit/drc_exclude.cells 71 additions, 0 deletionsopenlane/Control_Unit/drc_exclude.cells
- openlane/Control_Unit/no_synth.cells 201 additions, 0 deletionsopenlane/Control_Unit/no_synth.cells
- openlane/Control_Unit/pin_order.cfg 111 additions, 0 deletionsopenlane/Control_Unit/pin_order.cfg
- openlane/Memory_Controller/base_user_proj.sdc 3 additions, 0 deletionsopenlane/Memory_Controller/base_user_proj.sdc
- openlane/Memory_Controller/config.json 60 additions, 0 deletionsopenlane/Memory_Controller/config.json
- openlane/Memory_Controller/drc_exclude.cells 71 additions, 0 deletionsopenlane/Memory_Controller/drc_exclude.cells
- openlane/Memory_Controller/no_synth.cells 201 additions, 0 deletionsopenlane/Memory_Controller/no_synth.cells
- openlane/Memory_Controller/pin_order.cfg 111 additions, 0 deletionsopenlane/Memory_Controller/pin_order.cfg
- openlane/Wishbone_Slave_Controller/base_user_proj.sdc 3 additions, 0 deletionsopenlane/Wishbone_Slave_Controller/base_user_proj.sdc
- openlane/Wishbone_Slave_Controller/config.json 60 additions, 0 deletionsopenlane/Wishbone_Slave_Controller/config.json
- openlane/Wishbone_Slave_Controller/drc_exclude.cells 71 additions, 0 deletionsopenlane/Wishbone_Slave_Controller/drc_exclude.cells
- openlane/Wishbone_Slave_Controller/no_synth.cells 201 additions, 0 deletionsopenlane/Wishbone_Slave_Controller/no_synth.cells
- openlane/Wishbone_Slave_Controller/pin_order.cfg 111 additions, 0 deletionsopenlane/Wishbone_Slave_Controller/pin_order.cfg
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