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David Lanzendörfer
KnightMCU
Commits
c0572c28
Commit
c0572c28
authored
1 year ago
by
David Lanzendörfer
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Fix and add tools
parent
919564db
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Changes
3
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3 changed files
tools/make_sdc_entries.py
+1
-1
1 addition, 1 deletion
tools/make_sdc_entries.py
tools/make_sdc_entries_ctrl_unit.py
+23
-0
23 additions, 0 deletions
tools/make_sdc_entries_ctrl_unit.py
tools/make_sdc_entries_wb_slave_ctl.py
+54
-0
54 additions, 0 deletions
tools/make_sdc_entries_wb_slave_ctl.py
with
78 additions
and
1 deletion
tools/make_sdc_entries.py
+
1
−
1
View file @
c0572c28
...
...
@@ -11,7 +11,7 @@ commands = [
for
command
in
commands
:
for
i
in
range
(
3
1
):
for
i
in
range
(
3
2
):
print
(
command
+
"
[get_ports {data_i[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {data_o[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {addr_o[
"
+
str
(
i
)
+
"
]}]
"
)
...
...
This diff is collapsed.
Click to expand it.
tools/make_sdc_entries_ctrl_unit.py
0 → 100644
+
23
−
0
View file @
c0572c28
commands
=
[
"
set_input_delay -max 10 -clock [get_clocks \{clk\}]
"
,
"
set_input_delay -min 0 -clock [get_clocks \{clk\}]
"
,
"
set_input_transition -max 0.44
"
,
"
set_input_transition -min 0.05
"
,
"
set_output_delay -max 10 -clock [get_clocks \{clk\}]
"
,
"
set_output_delay -min 0 -clock [get_clocks \{clk\}]
"
,
"
set_load 0.14
"
]
for
command
in
commands
:
for
i
in
range
(
32
):
print
(
command
+
"
[get_ports {status[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {operation[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {reset}]
"
)
print
(
command
+
"
[get_ports {finished}]
"
)
print
(
command
+
"
[get_ports {matrix_mult_done}]
"
)
print
(
command
+
"
[get_ports {matrix_conv_done}]
"
)
print
(
command
+
"
[get_ports {multiplier_enable}]
"
)
print
(
command
+
"
[get_ports {convolution_enable}]
"
)
This diff is collapsed.
Click to expand it.
tools/make_sdc_entries_wb_slave_ctl.py
0 → 100644
+
54
−
0
View file @
c0572c28
commands
=
[
"
set_input_delay -max 10 -clock [get_clocks \{clk\}]
"
,
"
set_input_delay -min 0 -clock [get_clocks \{clk\}]
"
,
"
set_input_transition -max 0.44
"
,
"
set_input_transition -min 0.05
"
,
"
set_output_delay -max 10 -clock [get_clocks \{clk\}]
"
,
"
set_output_delay -min 0 -clock [get_clocks \{clk\}]
"
,
"
set_load 0.14
"
]
for
command
in
commands
:
#Wishbone
for
i
in
range
(
4
):
print
(
command
+
"
[get_ports {wb_sel_i[
"
+
str
(
i
)
+
"
]}]
"
)
for
i
in
range
(
32
):
print
(
command
+
"
[get_ports {wb_adr_i[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {wb_data_i[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {wb_data_o[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {wb_rst_i}]
"
)
print
(
command
+
"
[get_ports {wb_stb_i}]
"
)
print
(
command
+
"
[get_ports {wb_cyc_i}]
"
)
print
(
command
+
"
[get_ports {wb_we_i}]
"
)
print
(
command
+
"
[get_ports {wb_ack_o}]
"
)
# System stuff
print
(
command
+
"
[get_ports {reset}]
"
)
print
(
command
+
"
[get_ports {finished}]
"
)
for
i
in
range
(
32
):
print
(
command
+
"
[get_ports {status[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {operation[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {wbctrl_mem_addr[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {wbctrl_mem_data[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {sram_data[
"
+
str
(
i
)
+
"
]}]
"
)
for
i
in
range
(
2
):
print
(
command
+
"
[get_ports {wbctrl_mem_op[
"
+
str
(
i
)
+
"
]}]
"
)
for
i
in
range
(
3
):
print
(
command
+
"
[get_ports {irq[
"
+
str
(
i
)
+
"
]}]
"
)
for
i
in
range
(
128
):
print
(
command
+
"
[get_ports {la_data_in[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {la_data_out[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {la_oenb[
"
+
str
(
i
)
+
"
]}]
"
)
for
i
in
range
(
16
):
print
(
command
+
"
[get_ports {io_in[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {io_out[
"
+
str
(
i
)
+
"
]}]
"
)
print
(
command
+
"
[get_ports {io_oeb[
"
+
str
(
i
)
+
"
]}]
"
)
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Click to expand it.
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