Change some configs

openlane/AI_Accelerator_Top/config.json

@@ -30,16 +30,14 @@
     "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
     "NO_SYNTH_CELL_LIST": "dir::no_synth.cells",
     "DRC_EXCLUDE_CELL_LIST": "dir::drc_exclude.cells",
-    "PL_TARGET_DENSITY": 0.5,
+    "PL_TARGET_DENSITY": 0.2,
     "GRT_ALLOW_CONGESTION": true,
-    "GRT_OVERFLOW_ITERS": 100,
-    "ROUTING_OPT_ITERS": 100,
     "GRT_ANT_ITERS": 50,
     "GRT_ANT_MARGIN": 12,
-    "PL_RESIZER_SETUP_SLACK_MARGIN": 0.5,
+    "PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
     "PL_RESIZER_MAX_SLEW_MARGIN": 50,
     "GLB_RESIZER_MAX_SLEW_MARGIN": 50,
-    "GLB_RESIZER_SETUP_SLACK_MARGIN": 0.3,
+    "GLB_RESIZER_SETUP_SLACK_MARGIN": 0.2,
     "GRT_MAX_DIODE_INS_ITERS": 20,
     "GRT_ANT_ITERS": 20,
     "MAGIC_DEF_LABELS": 0,
@@ -53,28 +51,7 @@
     "IO_SYNC": 0,
     "BASE_SDC_FILE": "dir::base_user_proj.sdc",
     "DIODE_INSERTION_STRATEGY": 3,
-    "FP_PDN_CHECK_NODES": 0,
-    "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
-    "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
-    "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
-    "FP_PDN_ENABLE_RAILS": 0,
-    "DIODE_INSERTION_STRATEGY": 0,
-    "RUN_FILL_INSERTION": 0,
-    "RUN_TAP_DECAP_INSERTION": 0,
-    "FP_PDN_VPITCH": 180,
-    "FP_PDN_HPITCH": 180,
-    "CLOCK_TREE_SYNTH": 0,
-    "FP_PDN_VOFFSET": 5,
-    "FP_PDN_HOFFSET": 5,
-    "MAGIC_ZEROIZE_ORIGIN": 0,
-    "FP_SIZING": "absolute",
     "RUN_CVC": 0,
-    "FP_IO_VTHICKNESS_MULT": 4,
-    "FP_IO_HTHICKNESS_MULT": 4,
-    "FP_PDN_VWIDTH": 3.1,
-    "FP_PDN_HWIDTH": 3.1,
-    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
-    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
     "pdk::sky130*": {
         "FP_CORE_UTIL": 45,
         "RT_MAX_LAYER": "met4",

openlane/AI_Accelerator_Top/macro.cfg

-sram 1200 110 N
+sram 1000 100 N
 matrix_conv 300 760 W
 matrix_mult 1550 760 E

openlane/Matrix_Multiplication/pin_order.cfg

 #BUS_SORT
 
-#E
+#ER
 data_i\[0\]
 data_i\[1\]
 data_i\[2\]