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Commit 12a5f99b authored by David Lanzendörfer's avatar David Lanzendörfer
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Fix generation loop for Quartus

parent 9bf1d5d8
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module layer #( module layer #(
parameter NUMBER_SYNAPSES = `NUM_INPUT_SYNAPSES, parameter NUMBER_SYNAPSES = 8,
parameter NUMBER_NEURONS = `NUM_INPUT_NEURONS parameter NUMBER_NEURONS = 8
) )
( (
clk, clk,
...@@ -54,15 +54,19 @@ module layer #( ...@@ -54,15 +54,19 @@ module layer #(
wire[NUMBER_NEURONS-1:0][NUMBER_SYNAPSES-1:0] backprop_out_port_array; wire[NUMBER_NEURONS-1:0][NUMBER_SYNAPSES-1:0] backprop_out_port_array;
wire[NUMBER_SYNAPSES-1:0][NUMBER_NEURONS-1:0] backprop_out_port_array_flipped; wire[NUMBER_SYNAPSES-1:0][NUMBER_NEURONS-1:0] backprop_out_port_array_flipped;
for(gv1=0;gv1<NUMBER_NEURONS;gv1=gv1+1) begin generate
for(gv2=0;gv2<NUMBER_SYNAPSES;gv2=gv2+1) begin for(gv1=0;gv1<NUMBER_NEURONS;gv1=gv1+1) begin : flip_outer_loop
assign backprop_out_port_array_flipped[gv2][gv1] = backprop_out_port_array[gv1][gv2]; for(gv2=0;gv2<NUMBER_SYNAPSES;gv2=gv2+1) begin : flip_inner_loop
assign backprop_out_port_array_flipped[gv2][gv1] = backprop_out_port_array[gv1][gv2];
end
end end
end endgenerate
for(gv2=0;gv2<NUMBER_SYNAPSES;gv2=gv2+1) begin generate
assign backprop_out_port[gv2] = |backprop_out_port_array_flipped[gv2]; for(gv2=0;gv2<NUMBER_SYNAPSES;gv2=gv2+1) begin : backprop_loop
end assign backprop_out_port[gv2] = |backprop_out_port_array_flipped[gv2];
end
endgenerate
wire[NUMBER_NEURONS-1:0] inference_done_array; wire[NUMBER_NEURONS-1:0] inference_done_array;
assign inference_done = &inference_done_array; assign inference_done = &inference_done_array;
...@@ -71,19 +75,25 @@ module layer #( ...@@ -71,19 +75,25 @@ module layer #(
assign backprop_done = &backprop_done_array; assign backprop_done = &backprop_done_array;
wire [NUMBER_NEURONS-1:0][values_neuron+1:0]translated_address; wire [NUMBER_NEURONS-1:0][values_neuron+1:0]translated_address;
for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin generate
assign translated_address[gv] = address-gv*values_neuron; for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin : translate_addr
end assign translated_address[gv] = address-gv*values_neuron;
end
endgenerate
wire [NUMBER_NEURONS-1:0] read_enable_array; wire [NUMBER_NEURONS-1:0] read_enable_array;
for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin generate
assign read_enable_array[gv] = (translated_address[gv]<values_neuron) && read_enable; for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin : re_loop
end assign read_enable_array[gv] = (translated_address[gv]<values_neuron) && read_enable;
end
endgenerate
wire [NUMBER_NEURONS-1:0] write_enable_array; wire [NUMBER_NEURONS-1:0] write_enable_array;
for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin generate
assign write_enable_array[gv] = (translated_address[gv]<values_neuron) && write_enable; for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin : we_loop
end assign write_enable_array[gv] = (translated_address[gv]<values_neuron) && write_enable;
end
endgenerate
wire [NUMBER_NEURONS-1:0][31:0] data_o_array; wire [NUMBER_NEURONS-1:0][31:0] data_o_array;
wire [NUMBER_NEURONS-1:0] read_done_array; wire [NUMBER_NEURONS-1:0] read_done_array;
...@@ -110,37 +120,39 @@ module layer #( ...@@ -110,37 +120,39 @@ module layer #(
end end
genvar gv; genvar gv;
for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin generate
for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin : neurons
neuron #(
.NUMBER_SYNAPSES(NUMBER_SYNAPSES), neuron #(
.NUMBER_RNN_SYNAPSES(NUMBER_NEURONS) .NUMBER_SYNAPSES(NUMBER_SYNAPSES),
) .NUMBER_RNN_SYNAPSES(NUMBER_NEURONS)
ut( )
.clk(clk), ut(
.rst(rst), .clk(clk),
// Enable inference .rst(rst),
.run_inference(run_inference), // Enable inference
.inference_done(inference_done_array[gv]), .run_inference(run_inference),
// The data I/O .inference_done(inference_done_array[gv]),
.neuron_inputs(layer_inputs), // The data I/O
.neuron_output(layer_outputs[gv]), .neuron_inputs(layer_inputs),
.rnn_inputs(layer_outputs), .neuron_output(layer_outputs[gv]),
// Backprop .rnn_inputs(layer_outputs),
.backprop_out_port(backprop_out_port_array[gv]), // Backprop
.backprop_in_port(backprop_in_port), .backprop_out_port(backprop_out_port_array[gv]),
.backprop_done(backprop_done_array[gv]), .backprop_in_port(backprop_in_port),
.backprop_enable(backprop_enable), .backprop_done(backprop_done_array[gv]),
// Data interface .backprop_enable(backprop_enable),
.write_enable(write_enable_array[gv] ), // Data interface
.read_enable(read_enable_array[gv]), .write_enable(write_enable_array[gv] ),
.write_done(write_done_array[gv]), .read_enable(read_enable_array[gv]),
.read_done(read_done_array[gv]), .write_done(write_done_array[gv]),
.address(translated_address[gv]), .read_done(read_done_array[gv]),
.data_i(data_i), .address(translated_address[gv]),
.data_o(data_o_array[gv]) .data_i(data_i),
); .data_o(data_o_array[gv])
);
end end
endgenerate
endmodule endmodule
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