From 12a5f99b717ea76ab5e5d89231b800cee96026f8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <leviathan@libresilicon.com>
Date: Wed, 3 Jul 2024 14:11:29 +0100
Subject: [PATCH] Fix generation loop for Quartus
---
src/rtl/layer.sv | 110 ++++++++++++++++++++++++++---------------------
1 file changed, 61 insertions(+), 49 deletions(-)
diff --git a/src/rtl/layer.sv b/src/rtl/layer.sv
index 647f91a..6c42f71 100644
--- a/src/rtl/layer.sv
+++ b/src/rtl/layer.sv
@@ -1,6 +1,6 @@
module layer #(
- parameter NUMBER_SYNAPSES = `NUM_INPUT_SYNAPSES,
- parameter NUMBER_NEURONS = `NUM_INPUT_NEURONS
+ parameter NUMBER_SYNAPSES = 8,
+ parameter NUMBER_NEURONS = 8
)
(
clk,
@@ -54,15 +54,19 @@ module layer #(
wire[NUMBER_NEURONS-1:0][NUMBER_SYNAPSES-1:0] backprop_out_port_array;
wire[NUMBER_SYNAPSES-1:0][NUMBER_NEURONS-1:0] backprop_out_port_array_flipped;
- for(gv1=0;gv1<NUMBER_NEURONS;gv1=gv1+1) begin
- for(gv2=0;gv2<NUMBER_SYNAPSES;gv2=gv2+1) begin
- assign backprop_out_port_array_flipped[gv2][gv1] = backprop_out_port_array[gv1][gv2];
+ generate
+ for(gv1=0;gv1<NUMBER_NEURONS;gv1=gv1+1) begin : flip_outer_loop
+ for(gv2=0;gv2<NUMBER_SYNAPSES;gv2=gv2+1) begin : flip_inner_loop
+ assign backprop_out_port_array_flipped[gv2][gv1] = backprop_out_port_array[gv1][gv2];
+ end
end
- end
+ endgenerate
- for(gv2=0;gv2<NUMBER_SYNAPSES;gv2=gv2+1) begin
- assign backprop_out_port[gv2] = |backprop_out_port_array_flipped[gv2];
- end
+ generate
+ for(gv2=0;gv2<NUMBER_SYNAPSES;gv2=gv2+1) begin : backprop_loop
+ assign backprop_out_port[gv2] = |backprop_out_port_array_flipped[gv2];
+ end
+ endgenerate
wire[NUMBER_NEURONS-1:0] inference_done_array;
assign inference_done = &inference_done_array;
@@ -71,19 +75,25 @@ module layer #(
assign backprop_done = &backprop_done_array;
wire [NUMBER_NEURONS-1:0][values_neuron+1:0]translated_address;
- for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin
- assign translated_address[gv] = address-gv*values_neuron;
- end
+ generate
+ for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin : translate_addr
+ assign translated_address[gv] = address-gv*values_neuron;
+ end
+ endgenerate
wire [NUMBER_NEURONS-1:0] read_enable_array;
- for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin
- assign read_enable_array[gv] = (translated_address[gv]<values_neuron) && read_enable;
- end
+ generate
+ for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin : re_loop
+ assign read_enable_array[gv] = (translated_address[gv]<values_neuron) && read_enable;
+ end
+ endgenerate
wire [NUMBER_NEURONS-1:0] write_enable_array;
- for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin
- assign write_enable_array[gv] = (translated_address[gv]<values_neuron) && write_enable;
- end
+ generate
+ for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin : we_loop
+ assign write_enable_array[gv] = (translated_address[gv]<values_neuron) && write_enable;
+ end
+ endgenerate
wire [NUMBER_NEURONS-1:0][31:0] data_o_array;
wire [NUMBER_NEURONS-1:0] read_done_array;
@@ -110,37 +120,39 @@ module layer #(
end
genvar gv;
- for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin
-
- neuron #(
- .NUMBER_SYNAPSES(NUMBER_SYNAPSES),
- .NUMBER_RNN_SYNAPSES(NUMBER_NEURONS)
- )
- ut(
- .clk(clk),
- .rst(rst),
- // Enable inference
- .run_inference(run_inference),
- .inference_done(inference_done_array[gv]),
- // The data I/O
- .neuron_inputs(layer_inputs),
- .neuron_output(layer_outputs[gv]),
- .rnn_inputs(layer_outputs),
- // Backprop
- .backprop_out_port(backprop_out_port_array[gv]),
- .backprop_in_port(backprop_in_port),
- .backprop_done(backprop_done_array[gv]),
- .backprop_enable(backprop_enable),
- // Data interface
- .write_enable(write_enable_array[gv] ),
- .read_enable(read_enable_array[gv]),
- .write_done(write_done_array[gv]),
- .read_done(read_done_array[gv]),
- .address(translated_address[gv]),
- .data_i(data_i),
- .data_o(data_o_array[gv])
- );
+ generate
+ for(gv=0;gv<NUMBER_NEURONS;gv=gv+1) begin : neurons
+
+ neuron #(
+ .NUMBER_SYNAPSES(NUMBER_SYNAPSES),
+ .NUMBER_RNN_SYNAPSES(NUMBER_NEURONS)
+ )
+ ut(
+ .clk(clk),
+ .rst(rst),
+ // Enable inference
+ .run_inference(run_inference),
+ .inference_done(inference_done_array[gv]),
+ // The data I/O
+ .neuron_inputs(layer_inputs),
+ .neuron_output(layer_outputs[gv]),
+ .rnn_inputs(layer_outputs),
+ // Backprop
+ .backprop_out_port(backprop_out_port_array[gv]),
+ .backprop_in_port(backprop_in_port),
+ .backprop_done(backprop_done_array[gv]),
+ .backprop_enable(backprop_enable),
+ // Data interface
+ .write_enable(write_enable_array[gv] ),
+ .read_enable(read_enable_array[gv]),
+ .write_done(write_done_array[gv]),
+ .read_done(read_done_array[gv]),
+ .address(translated_address[gv]),
+ .data_i(data_i),
+ .data_o(data_o_array[gv])
+ );
- end
+ end
+ endgenerate
endmodule
--
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