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Manufacturing
Pearl River
Commits
c5dc4f26
Commit
c5dc4f26
authored
6 years ago
by
chipforge
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[DOC] Enlarge Document Structure
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Documents/LaTeX/principle_rsquare.tex
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c5dc4f26
%% ************ LibreSilicon's 1st TestWafer *******************
%%
%% Organisation: Chipforge
%% Germany / European Union
%%
%% Profile: Chipforge focus on fine System-on-Chip Cores in
%% Verilog HDL Code which are easy understandable and
%% adjustable. For further information see
%% www.chipforge.org
%% there are projects from small cores up to PCBs, too.
%%
%% File: PearlRiver/Documents/LaTeX/die_quarter.tex
%%
%% Purpose: Principle Description Pictgure for quarters
%%
%% ************ LaTeX with circdia.sty package ***************
%%
%% ///////////////////////////////////////////////////////////////////
%%
%% Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
%% All rights reserved.
%%
%% This Standard Cell Library is licensed under the Libre Silicon
%% public license; you can redistribute it and/or modify it under
%% the terms of the Libre Silicon public license as published by
%% the Libre Silicon alliance, either version 1 of the License, or
%% (at your option) any later version.
%%
%% This design is distributed in the hope that it will be useful,
%% but WITHOUT ANY WARRANTY; without even the implied warranty of
%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
%% See the Libre Silicon Public License for more details.
%%
%% ///////////////////////////////////////////////////////////////////
\begin{center}
Principle -
$
R
_
\square
$
\begin{figure}
[h]
\begin{center}
\begin{tikzpicture}
[]
% front
\draw
(0,0) -- (4,0) -- (4,1) -- (0,1) -- cycle;
% 1st top
\draw
(0,1) -- (2,3) -- (6,3) -- (4,1) -- cycle;
% 1st boarder
\draw
(4,0) -- (4,1) -- (6,3) -- (6,2) -- cycle;
% 2nd top
\draw
(2,3) -- (4,5) -- (8,5) -- (6,3) -- cycle;
% 2nd boarder
\draw
(6,3) -- (8,5) -- (8,4) -- (6,2) -- cycle;
\end{tikzpicture}
\end{center}
\end{figure}
\end{center}
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