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David Lanzendörfer
LCTime
Commits
0cad1ef0
Commit
0cad1ef0
authored
4 months ago
by
David Lanzendörfer
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Check for none statements
parent
b87032fc
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src/lctime/characterization/ngspice_subprocess.py
+31
-22
31 additions, 22 deletions
src/lctime/characterization/ngspice_subprocess.py
with
31 additions
and
22 deletions
src/lctime/characterization/ngspice_subprocess.py
+
31
−
22
View file @
0cad1ef0
...
...
@@ -138,20 +138,25 @@ def simulate_cell(
#assert False, "`voltage` must be either a float or {}".format(PieceWiseLinear)
# Create SPICE description of the input voltage sources.
active_signal_source_statements
=
"
\n
"
.
join
(
(
create_voltage_source_statement
(
net
,
wave
)
for
net
,
wave
in
input_voltages_active
.
items
()
vcc_statement
=
create_voltage_source_statement
(
net
,
wave
)
if
vcc_statement
not
None
:
active_signal_source_statements
=
"
\n
"
.
join
(
(
vcc_statement
for
net
,
wave
in
input_voltages_active
.
items
()
)
)
)
# Static inputs.
static_signal_source_statements
=
"
\n
"
.
join
(
(
create_voltage_source_statement
(
net
,
voltage
)
for
net
,
voltage
in
input_voltages_static
.
items
()
vcc_statement
=
create_voltage_source_statement
(
net
,
voltage
)
if
vcc_statement
not
None
:
static_signal_source_statements
=
"
\n
"
.
join
(
(
vcc_statement
for
net
,
voltage
in
input_voltages_static
.
items
()
)
)
)
# Load capacitance statements.
if
output_load_capacitances
is
None
:
...
...
@@ -554,24 +559,28 @@ def simulate_cell_v2(
return
f
"
V
{
net
}
{
net
}
{
ground_net
}
PWL(
{
voltage
.
to_spice_pwl_string
()
}
) DC=0
"
elif
isinstance
(
voltage
,
float
):
return
f
"
V
{
net
}
{
net
}
{
ground_net
}
{
voltage
}
"
else
:
assert
False
,
"
`voltage` must be either a float or {}
"
.
format
(
PieceWiseLinear
)
#
else:
#
assert False, "`voltage` must be either a float or {}".format(PieceWiseLinear)
# Create SPICE description of the input voltage sources.
active_signal_source_statements
=
"
\n
"
.
join
(
(
create_voltage_source_statement
(
net
,
wave
)
for
net
,
wave
in
input_voltages_active
.
items
()
vcc_statement
=
create_voltage_source_statement
(
net
,
wave
)
if
vcc_statement
not
None
:
active_signal_source_statements
=
"
\n
"
.
join
(
(
vcc_statement
for
net
,
wave
in
input_voltages_active
.
items
()
)
)
)
# Static inputs.
static_signal_source_statements
=
"
\n
"
.
join
(
(
create_voltage_source_statement
(
net
,
voltage
)
for
net
,
voltage
in
input_voltages_static
.
items
()
vcc_statement
=
create_voltage_source_statement
(
net
,
voltage
)
if
vcc_statement
not
None
:
static_signal_source_statements
=
"
\n
"
.
join
(
(
vcc_statement
for
net
,
voltage
in
input_voltages_static
.
items
()
)
)
)
# Load capacitance statements.
if
output_load_capacitances
is
None
:
...
...
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