Don't do that in here

Makefile

 # Parameters of network:
+
 NETWORK_PARAMS = \
 	NUM_INPUT_SYNAPSES:16 \
-	NUM_INPUT_NEURONS:5 \
+	NUM_INPUT_NEURONS:3 \
 	NUM_OUTPUT_NEURONS:16 \
-	NUM_HIDDEN_NEURONS_W:5 \
-	NUM_HIDDEN_NEURONS_H:6
+	NUM_HIDDEN_NEURONS_W:2 \
+	NUM_HIDDEN_NEURONS_H:2
+
+#NETWORK_PARAMS = \
+	NUM_INPUT_SYNAPSES:4 \
+	NUM_INPUT_NEURONS:3 \
+	NUM_OUTPUT_NEURONS:4 \
+	NUM_HIDDEN_NEURONS_W:2 \
+	NUM_HIDDEN_NEURONS_H:2
 
 TARGET_BOARD?=ecp5_minifpga
 
@@ -26,6 +34,7 @@ ifeq ($(TARGET_BOARD), ecp5_minifpga)
 	NEXTPNR=nextpnr-ecp5
 	TARGET=ecp5
 	BENCHES+=testbench_ecp5_minifpga.bin
+	CFGDIR=configs/ecp5
 	LPFILE=configs/ecp5/minifpga.lpf
 endif
 
@@ -72,12 +81,6 @@ obj_dir/V%__ALL.a: src/rtl/%.v src/rtl/params.vh
 	$(VERILATOR) $(CICD_VERILATOR_CFLAGS) --top-module $* -cc src/rtl/$*.v -Isrc/rtl
 	make -C obj_dir -f V$*.mk
 
-result/soc.json: result/firmware.hex src/rtl/params.vh result
-	yosys -s configs/synth.ys -p "synth_ecp5 -top soc -json $@" src/rtl/soc.v
-
-result/soc_out.config: $(LPFILE) # result/soc.json 
-	nextpnr-ecp5 --json result/soc.json --lpf $(LPFILE) --textcfg $@ --freq 50 --package CABGA256 --lpf-allow-unconstrained
-
 result/firmware.hex: result firmware/include/defines.h
 	make -C firmware firmware.hex
 	cp firmware/firmware.hex firmware.hex

configs/ecp5/README.md

-# ECP5 FPGAs available
-
-This folder contains the configs for the Altera FPGA boards I've tested
-the design with
-
-## Mini FPGA
-
-The Mini FPGA is an inexpensive FPGA I bought together with some motor drivers
-from AliExpress. The link can be found [here](https://www.aliexpress.com/item/1005004691760798.html)

configs/ecp5/minifpga.lpf

-
-#set_io flash_csb R12
-#set_io flash_clk R11
-#set_io flash_io0 P12
-#set_io flash_io1 P11
-#set_io flash_io2 T9
-#set_io flash_io3 P8
-
-LOCATE COMP "clk" SITE "E1";
-IOBUF PORT "clk" IO_TYPE=LVCMOS25;
-
-# TODO: Wire a flash chip to the board
-
-LOCATE COMP "leds[15]" SITE "L14";
-LOCATE COMP "leds[14]" SITE "L13";
-LOCATE COMP "leds[13]" SITE "G16";
-LOCATE COMP "leds[12]" SITE "G15";
-LOCATE COMP "leds[11]" SITE "F16";
-LOCATE COMP "leds[10]" SITE "F15";
-LOCATE COMP "leds[9]" SITE "D16";
-LOCATE COMP "leds[8]" SITE "D15";
-LOCATE COMP "leds[7]" SITE "C3";
-LOCATE COMP "leds[6]" SITE "A2";
-LOCATE COMP "leds[5]" SITE "B3";
-LOCATE COMP "leds[4]" SITE "A3";
-LOCATE COMP "leds[3]" SITE "B4";
-LOCATE COMP "leds[2]" SITE "A4";
-LOCATE COMP "leds[1]" SITE "B5";
-LOCATE COMP "leds[0]" SITE "A5";
-
-IOBUF PORT "leds[15]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[14]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[13]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[12]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[11]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[10]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[9]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[8]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[7]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[6]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[5]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[4]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[3]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[2]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[1]" IO_TYPE=LVCMOS25;
-IOBUF PORT "leds[0]" IO_TYPE=LVCMOS25;
-
-LOCATE COMP "uart_tx" SITE "F14";
-LOCATE COMP "uart_rx" SITE "F13";
-
-IOBUF PORT "uart_tx" IO_TYPE=LVCMOS25;
-IOBUF PORT "uart_rx" IO_TYPE=LVCMOS25;

configs/ecp5/openocd_minifpga.cfg

-#
-# Altera USB-Blaster
-#
-# http://www.altera.com/literature/ug/ug_usb_blstr.pdf
-#
-
-interface usb_blaster
-# These are already the defaults.
-# usb_blaster_vid_pid 0x09FB 0x6001
-# usb_blaster_device_desc "USB-Blaster"
-adapter_khz 3000

configs/synth.ys

-read_verilog -sv -Isrc/rtl -Isubmodules/picorv32 -Isubmodules/picorv32/picosoc src/rtl/soc.v
-hierarchy -top soc -libdir src/rtl -libdir submodules/picorv32 -libdir submodules/picorv32/picosoc