Design rules: GF180

Fix design rule violations of FETs

config.py

@@ -132,7 +132,7 @@ class Config:
 		return w
 
 	def get_layer_id(self, layer):
-		ret = (0, 0)
+		ret = None
 		if hasattr(self.tech_data, "output_map"):
 			if layer in self.tech_data.output_map:
 				ret = self.tech_data.output_map[layer]

fet.py

@@ -23,16 +23,19 @@ class FET(LibrePDKStructure):
 			self.well_layer_name = "nwell"
 			self.implant_layer_name = 'pdiffusion'
 			self.diff_contact_name = "pdiff_contact"
+			self.plus_layer_name = 'pplus'
 		elif mtype == ChannelType.NMOS:
 			self.well_layer_name = "pwell"
 			self.implant_layer_name = 'ndiffusion'
 			self.diff_contact_name = "ndiff_contact"
+			self.plus_layer_name = 'nplus'
 		else:
 			raise Exception("It has to be either NMOS or PMOS! This should NEVER happen!")
 
 		self.implant_layer = config.get_layer_id(self.implant_layer_name)
 		self.well_layer = config.get_layer_id(self.well_layer_name)
 		self.pdiff_contact_layer = config.get_layer_id(self.diff_contact_name)
+		self.plus_layer = config.get_layer_id(self.plus_layer_name)
 		via_size = self.config.get_via_size(self.diff_contact_name)
 
 		# those are LCLayout standard:
@@ -86,7 +89,7 @@ class FET(LibrePDKStructure):
 
 		# implant and taps
 		implant = gf.components.rectangle(size=(wi,hi), layer=self.implant_layer)
-		gate = gf.components.rectangle(size=(wp,hp), layer=self.gate_layer)
+		gate = gf.components.rectangle(size=(wp+2*gate_tap.xsize,hp), layer=self.gate_layer)
 
 		# determine well width/height
 		ww = gate_tap.xsize+wp+lph.to_nm(self.config, 2*me)
@@ -105,6 +108,12 @@ class FET(LibrePDKStructure):
 		well = gf.components.rectangle(size=(ww,hw), layer=self.well_layer)
 		self << well
 
+		if self.plus_layer is not None:
+			# Add the nplus/pplus
+			plus_size=gate_tap.xsize # This is wrong and needs to be calculated properly
+			plus = gf.components.rectangle(size=(ww+2*plus_size,hw+2*plus_size), layer=self.plus_layer)
+			self << plus.move([-plus_size,-plus_size])
+
 		if self.N > 1:
 			tap = gf.components.pad(size=s, layer=lid)
 			self.add_pin(2, self << tap)
@@ -116,12 +125,12 @@ class FET(LibrePDKStructure):
 		dy += drain_source_tap.ysize
 		self << implant.move([drain_source_tap.xsize-implant.xsize+mef, dy])
 
-		gy = dy+(implant.ysize-gate.ysize)/2
+		gy = dy+(implant.ysize-hp)/2
 
-		self.add_pin(1, self << gate_tap.move([mef+gate.xsize,gy]))
+		self.add_pin(1, self << gate_tap.move([mef+wp,gy]))
 		for i in range(self.N):
-			self << gate.move([mef,gy])
-			gy+=gate.ysize+drain_source_tap.ysize
+			self << gate.move([mef-gate_tap.xsize,gy])
+			gy+=hp+drain_source_tap.ysize
 
 		if self.N == 1:
 			dy += implant.ysize