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Commit f6f0b829 authored by chipforge's avatar chipforge
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Add another (captured) Schematic from another source

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Sources/geda/555_Righto-Version.sch 0 → 100644
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View file @ f6f0b829
v 20181211 2
C 40700 43700 1 180 0 asic-nmos-1.sym
{
T 39300 42900 5 8 0 0 180 0 1
device=NMOS_TRANSISTOR
T 39900 42900 5 10 1 1 180 0 1
refdes=M5
T 39900 43100 5 8 1 1 180 0 1
model-name=nmos4
T 39900 43400 5 8 1 0 180 0 1
w=1u
T 39900 43600 5 8 1 0 180 0 1
l=3u
}
C 39500 47000 1 0 0 asic-nmos-1.sym
{
T 40900 47800 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 40300 47800 5 10 1 1 0 0 1
refdes=M3
T 40300 47600 5 8 1 1 0 0 1
model-name=nmos4
T 40300 47300 5 8 1 0 0 0 1
w=1u
T 40300 47100 5 8 1 0 0 0 1
l=3u
}
C 42100 48000 1 180 0 asic-nmos-1.sym
{
T 40700 47200 5 8 0 0 180 0 1
device=NMOS_TRANSISTOR
T 41300 47200 5 10 1 1 180 0 1
refdes=M4
T 41300 47400 5 8 1 1 180 0 1
model-name=nmos4
T 41300 47700 5 8 1 0 180 0 1
w=1u
T 41300 47900 5 8 1 0 180 0 1
l=3u
}
C 40900 49100 1 0 0 asic-pmos-1.sym
{
T 42300 49900 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 41700 49900 5 10 1 1 0 0 1
refdes=M2
T 41700 49700 5 8 1 1 0 0 1
model-name=pmos4
T 41700 49400 5 8 1 0 0 0 1
w=10u
T 41700 49200 5 8 1 0 0 0 1
l=1u
}
C 40700 50100 1 180 0 asic-pmos-1.sym
{
T 39300 49300 5 8 0 0 180 0 1
device=PMOS_TRANSISTOR
T 39900 49300 5 10 1 1 180 0 1
refdes=M1
T 39900 49500 5 8 1 1 180 0 1
model-name=pmos4
T 39900 49800 5 8 1 0 180 0 1
w=10u
T 39900 50000 5 8 1 0 180 0 1
l=1u
}
T 50100 40900 9 14 1 0 0 0 1
T 50400 40100 9 10 1 0 0 0 1
1
T 52000 40100 9 10 1 0 0 0 1
1
T 53900 40100 9 10 1 0 0 0 1
C 37900 47400 1 0 0 input-2.sym
{
T 39300 47800 5 10 1 1 180 0 1
net=THRESHOLD
T 38500 48100 5 10 0 0 0 0 1
device=none
T 38400 47500 5 10 0 1 0 7 1
value=INPUT
}
C 49900 43500 1 90 0 input-2.sym
{
T 49500 44800 5 10 1 1 270 0 1
net=\_TRIGGER\_
T 49200 44100 5 10 0 0 90 0 1
device=none
T 49800 44000 5 10 0 1 90 7 1
value=INPUT
}
C 39900 50600 1 0 0 vdd-1.sym
N 40100 50600 40100 50400 4
N 40100 49100 40100 48000 4
C 40000 41200 1 0 0 gnd-1.sym
N 40100 42700 40100 41500 4
N 40100 43700 40100 47000 4
N 40200 47500 41400 47500 4
C 40700 47100 1 0 0 gnd-1.sym
N 40700 43200 44600 43200 4
C 42100 46600 1 270 0 io-1.sym
{
T 41900 47100 5 10 1 1 270 0 1
net=CONTROL_VOLTAGE
T 42700 46400 5 10 0 0 270 0 1
device=none
T 42200 45700 5 10 0 1 270 1 1
value=IO
}
N 41500 49100 41500 48000 4
N 40700 49600 40900 49600 4
N 40000 49600 39900 49600 4
N 39900 49600 39900 50400 4
N 39900 50400 57200 50400 4
N 41600 49600 41700 49600 4
N 41700 49600 41700 50400 4
N 40100 50100 40100 50400 4
N 41500 50100 41500 50400 4
N 40000 43200 39900 43200 4
N 39900 43200 39900 41700 4
N 39900 41700 40100 41700 4
N 40100 41700 57200 41700 4
N 40100 46800 41500 46800 4
C 42500 50200 1 270 0 asic-res-2.sym
{
T 42800 49000 5 8 0 0 270 0 1
device=RESISTOR
T 42800 50000 5 10 1 1 270 0 1
refdes=R1
T 42800 49500 5 10 1 1 270 0 1
value=1k
}
C 42500 44500 1 270 0 asic-res-2.sym
{
T 42800 43300 5 8 0 0 270 0 1
device=RESISTOR
T 42800 44300 5 10 1 1 270 0 1
refdes=R3
T 42800 43800 5 10 1 1 270 0 1
value=1k
}
C 42500 46500 1 270 0 asic-res-2.sym
{
T 42800 45300 5 8 0 0 270 0 1
device=RESISTOR
T 42800 46300 5 10 1 1 270 0 1
refdes=R2
T 42800 45800 5 10 1 1 270 0 1
value=1k
}
N 42600 49100 42600 46500 4
N 42600 45400 42600 44500 4
N 42600 41700 42600 43400 4
N 42600 50400 42600 50200 4
N 42100 47500 42600 47500 4
N 42200 47500 42200 46600 4
N 41500 47000 41500 46800 4
C 44000 42000 1 0 0 asic-nmos-1.sym
{
T 45400 42800 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 44800 42800 5 10 1 1 0 0 1
refdes=M6
T 44800 42600 5 8 1 1 0 0 1
model-name=nmos4
T 44800 42300 5 8 1 0 0 0 1
w=1u
T 44800 42100 5 8 1 0 0 0 1
l=3u
}
N 42600 45000 47100 45000 4
N 44600 41700 44600 42000 4
N 49700 45000 49800 45000 4
N 42900 42500 42900 41700 4
N 44700 42500 44900 42500 4
N 44900 42500 44900 41700 4
N 40800 47400 40800 47500 4
N 49800 45000 49800 44900 4
N 40100 48200 51500 48200 4
C 49700 44200 1 270 0 input-2.sym
{
T 49500 43600 5 10 1 1 270 0 1
net=\_RESET\_
T 50400 43600 5 10 0 0 270 0 1
device=none
T 49800 43700 5 10 0 1 270 7 1
value=INPUT
}
C 49900 42000 1 0 0 asic-nmos-1.sym
{
T 51300 42800 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 50700 42800 5 10 1 1 0 0 1
refdes=M28
T 50700 42600 5 8 1 1 0 0 1
model-name=nmos4
T 50700 42300 5 8 1 0 0 0 1
w=1u
T 50700 42100 5 8 1 0 0 0 1
l=3u
}
N 50500 41700 50500 42000 4
N 39300 47500 39500 47500 4
N 50500 43000 50500 46100 4
C 48500 46900 1 0 0 asic-pmos-1.sym
{
T 49900 47700 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 49300 47700 5 10 1 1 0 0 1
refdes=M15
T 49300 47500 5 8 1 1 0 0 1
model-name=pmos4
T 49300 47200 5 8 1 0 0 0 1
w=10u
T 49300 47000 5 8 1 0 0 0 1
l=1u
}
C 49900 46100 1 0 0 asic-pmos-1.sym
{
T 51300 46900 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 50700 46900 5 10 1 1 0 0 1
refdes=M20
T 50700 46700 5 8 1 1 0 0 1
model-name=pmos4
T 50700 46400 5 8 1 0 0 0 1
w=10u
T 50700 46200 5 8 1 0 0 0 1
l=1u
}
N 43200 46600 49900 46600 4
N 49100 50400 49100 47900 4
N 50500 50400 50500 47100 4
N 49400 47400 49400 50400 4
N 50600 46600 50800 46600 4
N 50800 46600 50800 50400 4
C 54700 46700 1 0 0 asic-pmos-1.sym
{
T 56100 47500 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 55500 47500 5 10 1 1 0 0 1
refdes=M22
T 55500 47300 5 8 1 1 0 0 1
model-name=pmos4
T 55500 47000 5 8 1 0 0 0 1
w=10u
T 55500 46800 5 8 1 0 0 0 1
l=1u
}
C 56400 46700 1 0 0 asic-pmos-1.sym
{
T 57800 47500 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 57200 47500 5 10 1 1 0 0 1
refdes=M30
T 57200 47300 5 8 1 1 0 0 1
model-name=pmos4
T 57200 47000 5 8 1 0 0 0 1
w=10u
T 57200 46800 5 8 1 0 0 0 1
l=1u
}
C 54700 44700 1 0 0 asic-nmos-1.sym
{
T 56100 45500 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 55500 45500 5 10 1 1 0 0 1
refdes=M27
T 55500 45300 5 8 1 1 0 0 1
model-name=nmos4
T 55500 45000 5 8 1 0 0 0 1
w=1u
T 55500 44800 5 8 1 0 0 0 1
l=3u
}
C 56400 44700 1 0 0 asic-nmos-1.sym
{
T 57800 45500 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 57200 45500 5 10 1 1 0 0 1
refdes=M31
T 57200 45300 5 8 1 1 0 0 1
model-name=nmos4
T 57200 45000 5 8 1 0 0 0 1
w=1u
T 57200 44800 5 8 1 0 0 0 1
l=3u
}
N 55300 46700 55300 45700 4
N 57000 46700 57000 45700 4
N 55300 44700 55300 41700 4
N 57000 44700 57000 41700 4
N 55400 45200 55500 45200 4
N 55500 45200 55500 41700 4
N 57100 45200 57200 45200 4
N 57200 45200 57200 41700 4
N 55900 42500 55900 47200 4
N 55900 45200 56400 45200 4
N 55900 47200 56400 47200 4
N 57000 46200 57400 46200 4
C 57400 46100 1 0 0 output-2.sym
{
T 57500 45900 5 10 1 1 0 0 1
net=OUTPUT
T 57600 46800 5 10 0 0 0 0 1
device=none
T 58300 46200 5 10 0 1 0 1 1
value=OUTPUT
}
C 57500 43100 1 0 0 io-1.sym
{
T 58500 43500 5 10 1 1 180 0 1
net=DISCHARGE
T 57700 43700 5 10 0 0 0 0 1
device=none
T 58400 43200 5 10 0 1 0 1 1
value=IO
}
N 56600 43200 57500 43200 4
N 56600 42000 56600 41700 4
N 57000 42500 56700 42500 4
N 55300 46200 55900 46200 4
N 55300 50400 55300 47700 4
N 57000 50400 57000 47700 4
N 55400 47200 55500 47200 4
N 55500 47200 55500 50400 4
N 57200 50400 57200 47200 4
N 57100 47200 57200 47200 4
T 53900 40400 9 10 1 0 0 0 1
B 40800 40100 8200 1300 19 10 1 0 -1 -1 0 -1 -1 -1 -1 -1
T 40900 40300 19 10 1 0 0 0 5
BOM:
dnw - D1
pmos4 - M1, M2, M8, M9, M10, M13, M14, M15, M16, M19, M20, M21, M22, M29, M30
nmos4 - M3, M4, M5, M6, M7, M11, M12, M17, M18, M23, M24, M25, M26, M27, M28, M31, M32
polyres - R1, R2, R3, R4
T 50100 40400 9 10 1 0 0 0 1
N 40800 49600 40800 48900 4
N 40800 48900 41500 48900 4
C 43800 43000 1 180 0 asic-nmos-1.sym
{
T 42400 42200 5 8 0 0 180 0 1
device=NMOS_TRANSISTOR
T 42900 42200 5 10 1 1 180 0 1
refdes=M7
T 42900 42400 5 8 1 1 180 0 1
model-name=nmos4
T 42900 42700 5 8 1 0 180 0 1
w=1u
T 42900 42900 5 8 1 0 180 0 1
l=3u
}
N 42900 42500 43100 42500 4
N 43800 42500 44000 42500 4
N 43900 42500 43900 43200 4
N 44600 43200 44600 43000 4
N 43200 42000 43200 41700 4
C 44500 49400 1 180 0 asic-pmos-1.sym
{
T 43100 48600 5 8 0 0 180 0 1
device=PMOS_TRANSISTOR
T 43700 48600 5 10 1 1 180 0 1
refdes=M10
T 43700 48800 5 8 1 1 180 0 1
model-name=pmos4
T 43700 49100 5 8 1 0 180 0 1
w=10u
T 43700 49300 5 8 1 0 180 0 1
l=1u
}
N 43900 50400 43900 49400 4
N 43700 50400 43700 48900 4
N 43700 48900 43800 48900 4
N 43900 48400 43900 43200 4
C 46000 50100 1 180 0 asic-pmos-1.sym
{
T 44600 49300 5 8 0 0 180 0 1
device=PMOS_TRANSISTOR
T 45300 49300 5 10 1 1 180 0 1
refdes=M9
T 45200 49500 5 8 1 1 180 0 1
model-name=pmos4
T 45200 49800 5 8 1 0 180 0 1
w=10u
T 45100 50000 5 8 1 0 180 0 1
l=1u
}
C 46200 49100 1 0 0 asic-pmos-1.sym
{
T 47600 49900 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 47000 49900 5 10 1 1 0 0 1
refdes=M8
T 46700 49700 5 8 1 1 0 0 1
model-name=pmos4
T 46700 49400 5 8 1 0 0 0 1
w=10u
T 47000 49200 5 8 1 0 0 0 1
l=1u
}
N 46000 49600 46200 49600 4
N 46100 49600 46100 48900 4
N 44500 48900 46100 48900 4
N 45400 48900 45400 49100 4
N 45200 50400 45200 49600 4
N 45200 49600 45300 49600 4
N 45400 50400 45400 50100 4
N 46800 50400 46800 50100 4
N 47000 50400 47000 49600 4
N 47000 49600 46900 49600 4
C 45300 43100 1 270 0 asic-res-2.sym
{
T 45600 41900 5 8 0 0 270 0 1
device=RESISTOR
T 45600 42900 5 10 1 1 270 0 1
refdes=R4
T 45600 42400 5 10 1 1 270 0 1
value=1k
}
N 45400 41700 45400 42000 4
C 46000 44200 1 180 0 asic-nmos-1.sym
{
T 44600 43400 5 8 0 0 180 0 1
device=NMOS_TRANSISTOR
T 45100 43400 5 10 1 1 180 0 1
refdes=M12
T 45100 43600 5 8 1 1 180 0 1
model-name=nmos4
T 45100 43900 5 8 1 0 180 0 1
w=1u
T 45100 44100 5 8 1 0 180 0 1
l=3u
}
C 46200 43200 1 0 0 asic-nmos-1.sym
{
T 47600 44000 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 47000 44000 5 10 1 1 0 0 1
refdes=M11
T 47000 43800 5 8 1 1 0 0 1
model-name=nmos4
T 47000 43500 5 8 1 0 0 0 1
w=1u
T 47000 43300 5 8 1 0 0 0 1
l=3u
}
N 45400 43200 45400 43100 4
N 45100 41700 45100 43700 4
N 45100 43700 45300 43700 4
N 46000 43700 46200 43700 4
N 46100 43700 46100 44400 4
N 46100 44400 46800 44400 4
N 46800 44200 46800 49100 4
N 46800 43200 46800 41700 4
N 47100 41700 47100 43700 4
N 47100 43700 46900 43700 4
N 45400 44200 45400 48900 4
C 48300 47900 1 180 0 asic-pmos-1.sym
{
T 46900 47100 5 8 0 0 180 0 1
device=PMOS_TRANSISTOR
T 47600 47100 5 10 1 1 180 0 1
refdes=M16
T 47500 47300 5 8 1 1 180 0 1
model-name=pmos4
T 47500 47600 5 8 1 0 180 0 1
w=10u
T 47400 47800 5 8 1 0 180 0 1
l=1u
}
N 49200 47400 49400 47400 4
N 48300 47400 48500 47400 4
N 47700 47900 47700 50400 4
N 47400 50400 47400 47400 4
N 47400 47400 47600 47400 4
N 48400 47400 48400 46600 4
N 47700 46600 47700 46900 4
N 43200 43000 43200 46600 4
C 47100 44500 1 0 0 asic-pmos-1.sym
{
T 48500 45300 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 47900 45300 5 10 1 1 0 0 1
refdes=M13
T 47600 45100 5 8 1 1 0 0 1
model-name=pmos4
T 47600 44800 5 8 1 0 0 0 1
w=10u
T 47900 44600 5 8 1 0 0 0 1
l=1u
}
C 49700 45500 1 180 0 asic-pmos-1.sym
{
T 48300 44700 5 8 0 0 180 0 1
device=PMOS_TRANSISTOR
T 49000 44700 5 10 1 1 180 0 1
refdes=M14
T 48900 44900 5 8 1 1 180 0 1
model-name=pmos4
T 48900 45200 5 8 1 0 180 0 1
w=10u
T 48800 45400 5 8 1 0 180 0 1
l=1u
}
N 49100 46900 49100 45500 4
N 47700 45500 47700 45700 4
N 47700 45700 49100 45700 4
C 48300 43000 1 180 0 asic-nmos-1.sym
{
T 46900 42200 5 8 0 0 180 0 1
device=NMOS_TRANSISTOR
T 47400 42200 5 10 1 1 180 0 1
refdes=M17
T 47400 42400 5 8 1 1 180 0 1
model-name=nmos4
T 47400 42700 5 8 1 0 180 0 1
w=1u
T 47400 42900 5 8 1 0 180 0 1
l=3u
}
C 48500 42000 1 0 0 asic-nmos-1.sym
{
T 49900 42800 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 49300 42800 5 10 1 1 0 0 1
refdes=M18
T 49300 42600 5 8 1 1 0 0 1
model-name=nmos4
T 49300 42300 5 8 1 0 0 0 1
w=1u
T 49300 42100 5 8 1 0 0 0 1
l=3u
}
N 47700 41700 47700 42000 4
N 47400 42500 47600 42500 4
N 48300 42500 48500 42500 4
N 49400 42500 49200 42500 4
N 47700 44500 47700 43000 4
N 47400 42500 47400 41700 4
N 49400 42500 49400 41700 4
N 49100 42000 49100 41700 4
N 49100 44500 49100 43000 4
N 47800 45000 49000 45000 4
C 48200 45200 1 0 0 vdd-1.sym
N 48400 45200 48400 45000 4
N 49800 42800 49800 42500 4
N 49800 42500 49900 42500 4
N 50800 41700 50800 42500 4
N 50800 42500 50600 42500 4
C 50700 42700 1 0 0 asic-nmos-1.sym
{
T 52100 43500 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 51500 43500 5 10 1 1 0 0 1
refdes=M26
T 51500 43300 5 8 1 1 0 0 1
model-name=nmos4
T 51500 43000 5 8 1 0 0 0 1
w=1u
T 51500 42800 5 8 1 0 0 0 1
l=3u
}
N 51300 42700 51300 41700 4
N 50700 43200 50500 43200 4
N 51600 41700 51600 43200 4
N 51600 43200 51400 43200 4
N 49100 43800 51500 43800 4
N 51300 43800 51300 43700 4
C 51500 43300 1 0 0 asic-nmos-1.sym
{
T 52900 44100 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 52300 44100 5 10 1 1 0 0 1
refdes=M25
T 52300 43900 5 8 1 1 0 0 1
model-name=nmos4
T 52300 43600 5 8 1 0 0 0 1
w=1u
T 52300 43400 5 8 1 0 0 0 1
l=3u
}
N 52100 43300 52100 41700 4
N 52400 41700 52400 43800 4
N 52400 43800 52200 43800 4
C 49600 40000 1 0 0 cvstitleblock-1.sym
{
T 50200 40400 5 10 1 1 0 0 1
date=2019-05-01
T 54100 40400 5 10 1 1 0 0 1
rev=$Revision$
T 54100 40100 5 10 1 1 0 0 1
auth=<CMOS-555@nospam.chipforge.org>
T 50200 40700 5 10 1 1 0 0 1
fname=555_Righto-Version.sch
T 53400 41100 5 14 1 1 0 4 1
title=CMOS "555" Timer IC - Schematic (Righto.com Version)
}
T 40900 39900 9 10 1 0 0 0 1
see http://righto.com/files/555c-schematic.pdf
C 51500 47700 1 0 0 asic-pmos-1.sym
{
T 52900 48500 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 52300 48500 5 10 1 1 0 0 1
refdes=M19
T 52300 48300 5 8 1 1 0 0 1
model-name=pmos4
T 52300 48000 5 8 1 0 0 0 1
w=10u
T 52300 47800 5 8 1 0 0 0 1
l=1u
}
C 56000 42000 1 0 0 asic-nmos-1.sym
{
T 57400 42800 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 56800 42800 5 10 1 1 0 0 1
refdes=M32
T 56800 42600 5 8 1 1 0 0 1
model-name=nmos4
T 56800 42300 5 8 1 0 0 0 1
w=1u
T 56800 42100 5 8 1 0 0 0 1
l=3u
}
N 55900 42500 56000 42500 4
N 56600 43200 56600 43000 4
N 52100 44300 52100 47700 4
N 52100 48700 52100 50400 4
N 52400 50400 52400 48200 4
N 52400 48200 52200 48200 4
C 50900 45400 1 0 0 asic-diode-1.sym
{
T 51900 46000 5 8 0 0 0 0 1
device=DIODE
T 51000 45900 5 10 1 1 0 0 1
refdes=D1
T 51500 45750 5 8 1 1 0 0 1
model-name=dnw
T 51000 45400 5 8 1 0 0 0 1
area=1e-12
}
N 50500 45700 50900 45700 4
N 51800 45700 52100 45700 4
C 53100 48900 1 0 0 asic-pmos-1.sym
{
T 54500 49700 5 8 0 0 0 0 1
device=PMOS_TRANSISTOR
T 53900 49700 5 10 1 1 0 0 1
refdes=M29
T 53600 49500 5 8 1 1 0 0 1
model-name=pmos4
T 53600 49200 5 8 1 0 0 0 1
w=10u
T 53900 49000 5 8 1 0 0 0 1
l=1u
}
C 54300 44200 1 180 0 asic-pmos-1.sym
{
T 52900 43400 5 8 0 0 180 0 1
device=PMOS_TRANSISTOR
T 53600 43400 5 10 1 1 180 0 1
refdes=M21
T 53500 43600 5 8 1 1 180 0 1
model-name=pmos4
T 53500 43900 5 8 1 0 180 0 1
w=10u
T 53400 44100 5 8 1 0 180 0 1
l=1u
}
C 53100 47700 1 0 0 asic-nmos-1.sym
{
T 54500 48500 5 8 0 0 0 0 1
device=NMOS_TRANSISTOR
T 53900 48500 5 10 1 1 0 0 1
refdes=M23
T 53900 48300 5 8 1 1 0 0 1
model-name=nmos4
T 53900 48000 5 8 1 0 0 0 1
w=1u
T 53900 47800 5 8 1 0 0 0 1
l=3u
}
C 54300 43000 1 180 0 asic-nmos-1.sym
{
T 52900 42200 5 8 0 0 180 0 1
device=NMOS_TRANSISTOR
T 53400 42200 5 10 1 1 180 0 1
refdes=M24
T 53400 42400 5 8 1 1 180 0 1
model-name=nmos4
T 53400 42700 5 8 1 0 180 0 1
w=1u
T 53400 42900 5 8 1 0 180 0 1
l=3u
}
N 53700 43200 53700 43000 4
N 53700 48900 53700 48700 4
N 54500 42500 54500 48800 4
N 54300 43700 54500 43700 4
N 54300 42500 54500 42500 4
N 52900 43100 52900 49400 4
N 53100 49400 52900 49400 4
N 53100 48200 52900 48200 4
C 53600 47000 1 0 0 gnd-1.sym
N 53700 47700 53700 47300 4
N 53800 48200 54000 48200 4
N 54000 48200 54000 47500 4
N 54000 47500 53700 47500 4
N 53600 42500 53400 42500 4
N 53400 42500 53400 41700 4
C 53500 44600 1 0 0 vdd-1.sym
N 53700 44600 53700 44200 4
N 53600 43700 53400 43700 4
N 53400 43700 53400 44400 4
N 53400 44400 53700 44400 4
N 53700 49900 53700 50400 4
N 53800 49400 54000 49400 4
N 54000 49400 54000 50400 4
N 53700 42000 53700 41700 4
N 52900 45700 52100 45700 4
N 52900 43100 53700 43100 4
N 54700 47200 54500 47200 4
N 54500 45200 54700 45200 4
N 53700 48800 54500 48800 4
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