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Commit 0d337937 authored by chipforge's avatar chipforge
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Update pad cell list, use CircDia for Schematics

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Documentation/LaTeX/PADANA_schematic.tex 0 → 100644
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View file @ 0d337937
\begin{center}
Schematic of \textbf{PADANA} cell
\begin{figure}[h]
\begin{center}
\begin{circuitdiagram}{9}{33}
% pad
\pin[\male]{8}{16}{R}{PAD}
\pin{1}{16}{L}{IO} % pin IO
\wire{2}{16}{7}{16}
\junct{6}{16}
% pull-up mosfet
\power{1}{31.5}{U}{VDDIO} % power on gate
\wire{1}{31}{1}{29}
\trans[\wireUD{0.5}]{penh*}{4}{27.5}{R}{}{}
\power{6}{31.5}{U}{} % power above pull-up
% pull-down mosfet
\ground{1}{0.5}{D} % ground on gate
\wire{1}{1}{1}{3}
\trans[\wireUD{0.5}]{nenh*}{4}{4.5}{R}{}{}
\ground{6}{0.5}{D} % ground below pull-down
% pad connectivity
\wire{6}{7}{6}{25}
\end{circuitdiagram}
\end{center}
\end{figure}
\end{center}
Documentation/LaTeX/PADCIN_circuit.tex 0 → 100644
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\begin{center}
Schematic of \textbf{PADCIN} cell
\begin{figure}[h]
\begin{center}
\begin{circuitdiagram}{17}{10}
% pad
\pin[\male]{16}{3}{R}{PAD}
% input channel
\gate[\schmitt]{not}{12}{3}{L}{}{} % input schmitt-trigger
\gate[\inputs{2}]{nor}{6}{5}{L}{}{}% input enable
\pin{1}{5}{L}{DI} % pin input
\pin{1}{9}{L}{IEN} % pin input enable
\wire{2}{9}{9}{9}
\wire{9}{9}{9}{7}
\end{circuitdiagram}
\end{center}
\end{figure}
\end{center}
Documentation/LaTeX/PADCOUT_circuit.tex 0 → 100644
+ 19
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\begin{center}
Schematic of \textbf{PADCOUT} cell
\begin{figure}[h]
\begin{center}
\begin{circuitdiagram}{16}{7}
% pad
\pin[\male]{15}{4}{R}{PAD}
% 1st buffer stage
\usgate
\pin{1}{4}{L}{DO} % pin output
\gate{not}{5}{4}{R}{}{}% buffer
% 2nd buffer stage
\pin{1}{1}{L}{OE} % pin output enable [0]
\wire{2}{1}{11}{1}
\gate[\tristate{Dp}]{not}{11}{4}{Rc}{}{} % buffer
\end{circuitdiagram}
\end{center}
\end{figure}
\end{center}
Documentation/LaTeX/PADGIO_circuit.tex 0 → 100644
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View file @ 0d337937
\begin{center}
Schematic of \textbf{PADGIO} cell
\begin{figure}[h]
\begin{center}
\begin{circuitdiagram}{24}{33}
% pad
\pin[\male]{23}{16}{R}{PAD}
\wire{16}{16}{22}{16}
\junct{16}{16}
\wire{21}{13}{21}{19}
\junct{21}{16}
% pull-up mosfet
\trans[\wireUD{0.5}]{penh*}{19}{27.5}{R}{}{pull-up}
\power{21}{31.5}{U}{} % power above pull-up
\pin{1}{29}{L}{PUN} % pin pull-up enable
\wire{2}{29}{16}{29}
\resis{21}{22}{Vlr}{}{100k}
% pull-down mosfet
\trans[\wireUD{0.5}]{nenh*}{19}{4.5}{R}{pull-down}{}
\ground{21}{0.5}{D} % ground below pull-down
\pin{1}{3}{L}{PD} % pin pull-down enable
\wire{2}{3}{16}{3}
\resis{21}{10}{Vlr}{}{100k}
% 1st buffer stage
\usgate
\pin{1}{11}{L}{DO} % pin output
\gate{not}{5}{11}{R}{}{}% buffer
\wire{8}{11}{9}{11} % ->
\junct{9}{11} % between buffers
\wire{9}{8}{9}{14}
% 2nd buffer stage, 1x
\pin{1}{5}{L}{OE[0]} % pin output enable [0]
\wire{2}{5}{12}{5}
\gate[\tristate{Dp}]{not}{12}{8}{Rc}{}{1} % buffer
\wire{15}{8}{16}{8}
% 2nd buffer stage, 2x
\pin{1}{17}{L}{OE[1]} % pin output enable [1]
\wire{2}{17}{12}{17}
\gate[\tristate{Up}]{not}{12}{14}{Rc}{}{2} % buffer
\wire{15}{14}{16}{14}
% pad connectivity
\wire{16}{8}{16}{21}
\junct{16}{14} % between buffers
% input channel
\wire{15}{21}{16}{21}
\gate[\schmitt]{not}{12}{21}{L}{}{} % input schmitt-trigger
\gate[\inputs{2}]{nor}{6}{23}{L}{}{}% input enable
\pin{1}{23}{L}{DI} % pin input
\pin{1}{27}{L}{IEN} % pin input enable
\wire{2}{27}{9}{27}
\wire{9}{27}{9}{25}
\end{circuitdiagram}
\end{center}
\end{figure}
\end{center}
Documentation/LaTeX/PADGND_schematic.tex 0 → 100644
+ 22
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View file @ 0d337937
\begin{center}
Schematic of \textbf{PADGND} cell
\begin{figure}[h]
\begin{center}
\begin{circuitdiagram}{9}{33}
% pad
\pin[\male]{1}{16}{L}{PAD}
\pin{8}{16}{R}{GND} % pin GND
\wire{2}{16}{7}{16}
\junct{6}{16}
% pull-up mosfet
\power{1}{31.5}{U}{} % power on gate
\wire{1}{31}{1}{29}
\trans[\wireUD{0.5}]{penh*}{4}{27.5}{R}{}{}
\power{6}{31.5}{U}{} % power above pull-up
\ground{6}{0.5}{D} % ground below pull-down
% pad connectivity
\wire{6}{1}{6}{25}
\end{circuitdiagram}
\end{center}
\end{figure}
\end{center}
Documentation/LaTeX/PADOC_circuit.tex 0 → 100644
+ 37
− 0
View file @ 0d337937
\begin{center}
Schematic of \textbf{PADOC} cell
\begin{figure}[h]
\begin{center}
\begin{circuitdiagram}{19}{25}
% pad
\pin[\male]{18}{12}{R}{PAD}
\wire{16}{12}{17}{12}
% 1st buffer stage
\usgate
\pin{1}{12}{L}{DO} % pin output
\gate{not}{5}{12}{R}{}{} % buffer
\wire{8}{12}{9}{12} % ->
\junct{9}{12} % between buffers
\wire{9}{3}{9}{21}
% 2nd buffer stage, 1x
\pin{1}{6}{L}{OE[0]} % pin output enable [0]
\wire{2}{6}{12}{6}
\gate[\tristate{Up}]{not}{12}{3}{R}{3mA}{} % buffer
\wire{15}{3}{16}{3}
% 2nd buffer stage, 2x
\pin{1}{15}{L}{OE[1]} % pin output enable [1]
\wire{2}{15}{12}{15}
\gate[\tristate{Up}]{not}{12}{12}{R}{6mA}{} % buffer
\wire{15}{12}{16}{12}
% 2nd buffer stage, 4x
\pin{1}{24}{L}{OE[2]} % pin output enable [1]
\wire{2}{24}{12}{24}
\gate[\tristate{Up}]{not}{12}{21}{R}{12mA}{} % buffer
\wire{15}{21}{16}{21}
% pad connectivity
\wire{16}{3}{16}{21}
\junct{16}{12} % between buffers
\end{circuitdiagram}
\end{center}
\end{figure}
\end{center}
Documentation/LaTeX/PADTIN_circuit.tex 0 → 100644
+ 18
− 0
View file @ 0d337937
\begin{center}
Schematic of \textbf{PADTIN} cell
\begin{figure}[h]
\begin{center}
\begin{circuitdiagram}{17}{10}
% pad
\pin[\male]{16}{3}{R}{PAD}
% input channel
\gate[\schmitt]{not}{12}{3}{L}{}{} % input schmitt-trigger
\gate[\inputs{2}]{nor}{6}{5}{L}{}{}% input enable
\pin{1}{5}{L}{DI} % pin input
\pin{1}{9}{L}{IEN} % pin input enable
\wire{2}{9}{9}{9}
\wire{9}{9}{9}{7}
\end{circuitdiagram}
\end{center}
\end{figure}
\end{center}
Documentation/LaTeX/PADTOUT_circuit.tex 0 → 100644
+ 19
− 0
View file @ 0d337937
\begin{center}
Schematic of \textbf{PADTOUT} cell
\begin{figure}[h]
\begin{center}
\begin{circuitdiagram}{16}{7}
% pad
\pin[\male]{15}{4}{R}{PAD}
% 1st buffer stage
\usgate
\pin{1}{4}{L}{DO} % pin output
\gate{not}{5}{4}{R}{}{}% buffer
% 2nd buffer stage
\pin{1}{1}{L}{OE} % pin output enable [0]
\wire{2}{1}{11}{1}
\gate[\tristate{Dp}]{not}{11}{4}{Rc}{}{} % buffer
\end{circuitdiagram}
\end{center}
\end{figure}
\end{center}
Documentation/LaTeX/PADVDD_schematic.tex 0 → 100644
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− 0
View file @ 0d337937
\begin{center}
Schematic of \textbf{PADVDD} cell
\begin{figure}[h]
\begin{center}
\begin{circuitdiagram}{9}{33}
% pad
\pin[\male]{1}{16}{L}{PAD}
\pin{8}{16}{R}{VDD} % pin VDD
\wire{2}{16}{7}{16}
\junct{6}{16}
\power{6}{31.5}{U}{} % power above pull-up
% pull-down mosfet
\ground{1}{0.5}{D} % ground on gate
\wire{1}{1}{1}{3}
\trans[\wireUD{0.5}]{nenh*}{4}{4.5}{R}{}{}
\ground{6}{0.5}{D} % ground below pull-down
% pad connectivity
\wire{6}{7}{6}{31}
\end{circuitdiagram}
\end{center}
\end{figure}
\end{center}
Documentation/LaTeX/ls1u-padcells.pdf
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Documentation/LaTeX/ls1u-padcells.tex
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View file @ 0d337937
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