diff --git a/Documents/LaTeX/GNUmakefile b/Documents/LaTeX/GNUmakefile
new file mode 100644
index 0000000000000000000000000000000000000000..8ed680b7c774c1e3459997a10db918f3de9231a0
--- /dev/null
+++ b/Documents/LaTeX/GNUmakefile
@@ -0,0 +1,94 @@
+# ************ LibreSilicon's 1st TestWafer *******************
+#
+# Organisation: Chipforge
+# Germany / European Union
+#
+# Profile: Chipforge focus on fine System-on-Chip Cores in
+# Verilog HDL Code which are easy understandable and
+# adjustable. For further information see
+# www.chipforge.org
+# there are projects from small cores up to PCBs, too.
+#
+# File: PearlRiver/Documents/LaTeX/GNUmakefile
+#
+# Purpose: Makefile for Document Generation in LaTeX
+#
+# ************ GNU Make 3.80 Source Code ****************
+#
+# ////////////////////////////////////////////////////////////////
+#
+# Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
+# All rights reserved.
+#
+# This Standard Cell Library is licensed under the Libre Silicon
+# public license; you can redistribute it and/or modify it under
+# the terms of the Libre Silicon public license as published by
+# the Libre Silicon alliance, either version 1 of the License, or
+# (at your option) any later version.
+#
+# This design is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+# See the Libre Silicon Public License for more details.
+#
+# ////////////////////////////////////////////////////////////////////
+
+# project name
+
+PROJECT = PearlRiver
+
+# directory pathes
+
+DOCUMENTSDIR = .
+OUTPUTDIR = ..
+
+# tool variables
+
+CAT ?= @cat
+ECHO ?= @echo # -e
+MV ?= mv
+TAR ?= rm -f
+TAR ?= tar -zh
+DATE := $(shell date +%Y%m%d)
+
+# project tools
+
+LATEX ?= pdflatex -output-directory $(OUTPUTDIR)
+RUBBER ?= rubber
+
+# ----------------------------------------------------------------
+# DEFAULT TARGETS
+# ----------------------------------------------------------------
+
+# display help screen if no target is specified
+
+.PHONY: help
+help:
+ $(ECHO) "-------------------------------------------------------------------"
+ $(ECHO) " available targets:"
+ $(ECHO) "-------------------------------------------------------------------"
+ $(ECHO) ""
+ $(ECHO) " help - print this help screen"
+ $(ECHO) " clean - clean up all intermediate files"
+ $(ECHO) ""
+ $(ECHO) " doc - compile documentation"
+ $(ECHO) ""
+
+
+.PHONY: clean
+clean:
+ $(RM) *.aux *.idx *.log *.toc *.out
+
+# ----------------------------------------------------------------
+# DOCUMENTATION TARGETS
+# ----------------------------------------------------------------
+
+.PHONY: doc
+doc: pdf clean
+
+.PHONY: pdf
+pdf: $(PROJECT).tex revision.tex
+ $(LATEX) $<
+
+%.pdf: %.tex
+ $(RUBBER) -m pdftex $<
diff --git a/Documents/LaTeX/teststructures.tex b/Documents/LaTeX/teststructures.tex
new file mode 100644
index 0000000000000000000000000000000000000000..7500e341fc2169b8a326189e0dbb2e26ac6be841
--- /dev/null
+++ b/Documents/LaTeX/teststructures.tex
@@ -0,0 +1,62 @@
+%% ************ LibreSilicon's 1st TestWafer *******************
+%%
+%% Organisation: Chipforge
+%% Germany / European Union
+%%
+%% Profile: Chipforge focus on fine System-on-Chip Cores in
+%% Verilog HDL Code which are easy understandable and
+%% adjustable. For further information see
+%% www.chipforge.org
+%% there are projects from small cores up to PCBs, too.
+%%
+%% File: PearlRiver/Documents/LaTeX/teststructures.tex
+%%
+%% Purpose: Chapter File for Test Structures
+%%
+%% ************ LaTeX with circdia.sty package ***************
+%%
+%% ///////////////////////////////////////////////////////////////////
+%%
+%% Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
+%% All rights reserved.
+%%
+%% This Standard Cell Library is licensed under the Libre Silicon
+%% public license; you can redistribute it and/or modify it under
+%% the terms of the Libre Silicon public license as published by
+%% the Libre Silicon alliance, either version 1 of the License, or
+%% (at your option) any later version.
+%%
+%% This design is distributed in the hope that it will be useful,
+%% but WITHOUT ANY WARRANTY; without even the implied warranty of
+%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+%% See the Libre Silicon Public License for more details.
+%%
+%% ///////////////////////////////////////////////////////////////////
+\section{Test Structures}
+
+\subsection{Metall and Poly Resistance}
+
+% wells
+% stripes
+% pad
+
+\subsection{Contact and Via Resistance}
+
+\subsection{Layer Capacitance}
+
+\subsection{Diodes}
+
+% parasitic diodes, Zener diodes
+
+\subsection{p-channel and n-channels Transistors}
+
+% p-/n- Tables
+
+\subsection{Bipolar Junctions Transistors}
+
+\subsection{Experimental}
+
+% High-Voltage Fets
+% SONOS
+
+\clearpage
diff --git a/GNUmakefile b/GNUmakefile
index 16b2d0dc3069516af2e9d9f0a37038fc42e7b450..fbf06f9ca2b653ad144fb410119d9fcb479529cc 100644
--- a/GNUmakefile
+++ b/GNUmakefile
@@ -54,7 +54,7 @@ DATE := $(shell date +%Y%m%d)
# project tools
-LATEX ?= pdflatex -output-directory $(DOCUMENTSDIR) $(OUTPUTDIR)
+# ??
# default
@@ -96,13 +96,14 @@ dist: clean
.PHONY: clean
clean:
$(ECHO) "---- clean up all intermediate files ----"
- $(MAKE) -C $(DOCUMENTSDIR)/LaTeX -f build.mk $@
+ $(MAKE) -C $(DOCUMENTSDIR)/LaTeX -f GNUmakefile $@
# ----------------------------------------------------------------
# DOCUMENTATION TARGETS
# ----------------------------------------------------------------
.PHONY: doc
-doc: $(DOCUMENTSDIR)/LaTeX/$(PROJECT).tex $(DOCUMENTSDIR)/LaTeX/revision.tex
- TEXINPUTS=$$TEXINPUT:./$(DOCUMENTSDIR)/LaTeX $(LATEX) $(<F)
-# TEXINPUTS=::../../circdia xelatex PearlRiver.tex
+doc:
+ $(MAKE) -C $(DOCUMENTSDIR)/LaTeX -f GNUmakefile $@
+
+