diff --git a/Documents/LaTeX/GNUmakefile b/Documents/LaTeX/GNUmakefile
new file mode 100644
index 0000000000000000000000000000000000000000..7da7aeabd33346d0f857cfe364c42f29bffad9ea
--- /dev/null
+++ b/Documents/LaTeX/GNUmakefile
@@ -0,0 +1,92 @@
+# ************ LibreSilicon's 1st TestWafer *******************
+#
+# Organisation: Chipforge
+# Germany / European Union
+#
+# Profile: Chipforge focus on fine System-on-Chip Cores in
+# Verilog HDL Code which are easy understandable and
+# adjustable. For further information see
+# www.chipforge.org
+# there are projects from small cores up to PCBs, too.
+#
+# File: PearlRiver/Documents/LaTeX/GNUmakefile
+#
+# Purpose: Makefile for Document Generation in LaTeX
+#
+# ************ GNU Make 3.80 Source Code ****************
+#
+# ////////////////////////////////////////////////////////////////
+#
+# Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
+# All rights reserved.
+#
+# This Standard Cell Library is licensed under the Libre Silicon
+# public license; you can redistribute it and/or modify it under
+# the terms of the Libre Silicon public license as published by
+# the Libre Silicon alliance, either version 1 of the License, or
+# (at your option) any later version.
+#
+# This design is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+# See the Libre Silicon Public License for more details.
+#
+# ////////////////////////////////////////////////////////////////////
+
+# project name
+
+PROJECT = PearlRiver
+
+# directory pathes
+
+DOCUMENTSDIR = .
+OUTPUTDIR = ..
+
+# tool variables
+
+CAT ?= @cat
+ECHO ?= @echo # -e
+MV ?= mv
+RM ?= rm -f
+TAR ?= tar -zh
+DATE := $(shell date +%Y%m%d)
+
+# project tools
+
+LATEX ?= lualatex
+
+# ----------------------------------------------------------------
+# DEFAULT TARGETS
+# ----------------------------------------------------------------
+
+# display help screen if no target is specified
+
+.PHONY: help
+help:
+ $(ECHO) "-------------------------------------------------------------------"
+ $(ECHO) " available targets:"
+ $(ECHO) "-------------------------------------------------------------------"
+ $(ECHO) ""
+ $(ECHO) " help - print this help screen"
+ $(ECHO) " clean - clean up all intermediate files"
+ $(ECHO) ""
+ $(ECHO) " doc - compile documentation"
+ $(ECHO) ""
+
+
+.PHONY: clean
+clean:
+ $(RM) *.aux *.idx *.log *.toc *.out
+
+# ----------------------------------------------------------------
+# DOCUMENTATION TARGETS
+# ----------------------------------------------------------------
+
+.PHONY: doc
+doc: pdf clean
+
+.PHONY: pdf
+pdf: $(PROJECT).tex revision.tex
+ $(LATEX) $<
+ $(LATEX) $<
+ $(MV) $(PROJECT).pdf $(OUTPUTDIR)
diff --git a/Documents/LaTeX/PearlRiver.tex b/Documents/LaTeX/PearlRiver.tex
index 75e2bc66aac5d30fbde17eee83887e6d4756ed3c..08090f4dc699bd4174dca03e5c3500ecb6111409 100644
--- a/Documents/LaTeX/PearlRiver.tex
+++ b/Documents/LaTeX/PearlRiver.tex
@@ -13,7 +13,7 @@
%%
%% Purpose: Top Level File for 1st Test Wafer Documentation
%%
-%% ************ LaTeX with circdia.sty package ***************
+%% ************ LuaLaTeX with circdia.sty package ***************
%%
%% ///////////////////////////////////////////////////////////////////
%%
@@ -32,48 +32,65 @@
%% See the Libre Silicon Public License for more details.
%%
%% ///////////////////////////////////////////////////////////////////
-\documentclass[10pt,a4paper,twoside]{article}
-\usepackage[utf8]{inputenc}
-\usepackage[english]{babel}
-\usepackage{CJK}
-%\usepackage{amsmath}
-%\usepackage{amsfonts}
+\documentclass[a4paper,english,twoside]{article}
+\usepackage{fontspec}
\usepackage{amssymb}
-%\usepackage{gensymb}
-%\usepackage{graphicx}
+\usepackage{mathtools}
+\usepackage{babel}
+\usepackage{luatexja-fontspec}
\usepackage[digital,srcmeas,semicon]{circdia}
-% \usepackage[dvipsnames]{xcolor}
-\usepackage[left=2cm,right=2cm,top=2cm,bottom=2cm]{geometry}
+\usepackage[left=2cm,right=2cm,top=1.5cm,bottom=3cm]{geometry}
-\title{LibreSilicon's 1st Test Wafer \begin{CJK}{UTF8}{gbsn}\\(ç 江芯片一å·) \end{CJK}}
+\defaultfontfeatures{Ligatures=TeX}
+%\setmainfont{Linux Libertine 0}
+\setmainjfont{FandolSong}
+%\setsansfont{Kurier}
+%\setsansfont{Menlo}
+
+\title{PearlRiver -- LibreSilicon's 1st Test Wafer (ç 江芯片一å·)}
\author{Hagen Sankowski}
\date{\today}
\makeindex % usefull for ToC
-\setlength{\parindent}{0pt} % get rid of annoying indents
+\setlength{\parindent}{0em} % get rid of annoying indents
+\setlength{\parskip}{0.5em}
\begin{document}
\maketitle
+
\begin{abstract}
\begin{quote}
-Copyright \textcopyright 2018 CHIPFORGE.ORG. All rights reserved.
+Copyright \textcopyright 2018 CHIPFORGE.ORG. All rights reserved. \\
-This process is licensed under the Libre Silicon public license; you can redistribute it and/or modify it under the terms of the Libre Silicon public license as published by the Libre Silicon alliance either version 2 of the License, or (at your option) any later version.
+This process is licensed under the Libre Silicon public license; you can redistribute it and/or modify it under the terms of the Libre Silicon public license as published by the Libre Silicon alliance either version 1 of the License, or (at your option) any later version. \\
-This design is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the Libre Silicon Public License for more details.
+This design is distributed in the hope that it will be useful, but \textsc{WITHOUT ANY WARRANTY}; without even the implied warranty of \textsc{MERCHANTABILITY} or \textsc{FITNESS FOR A PARTICULAR PURPOSE}. See the Libre Silicon Public License for more details. \\
For further clarification consult the complete documentation of the process.
\end{quote}
\end{abstract}
+\clearpage
\input{revision.tex}
+PearlRiver is the first Test Wafer for the LibreSilicon 1 $ \mu m$ Technology.
+
+This Testwafer contains almost all test structures to evaulate and qualify the technology-depended parameters.
+On Wafer are placed structures to measure the sheet-resistance of all Poly and Metal Layer, as well Capacitors, NMOS and PMOS Transistors, Bipolar Junction Transistors, Diodes and Flash cells.
+There are even common cells like NANDs, NORs and Inverters forming ring oscillators.
+
+All parameters, measured from all test structures are used for Spice3f simulation models.
+
\clearpage
\tableofcontents
\clearpage
\pagestyle{headings}
+\renewcommand{\theequation}{\thesection.\arabic{equation}}
+\numberwithin{equation}{section}
\input{considerations.tex}
\input{ringoscillators.tex}
+\input{teststructures.tex}
+
\end{document}
diff --git a/Documents/LaTeX/considerations.tex b/Documents/LaTeX/considerations.tex
index b3d21ad729c385276ff7cbc7cac44b62e59f7c0b..841699989573a39e9c1792b1d9a307fa61af8c33 100644
--- a/Documents/LaTeX/considerations.tex
+++ b/Documents/LaTeX/considerations.tex
@@ -34,26 +34,61 @@
%% ///////////////////////////////////////////////////////////////////
\section{Considerations}
-PearlRiver is the first Testwafer for the LibreSilicon 1 $ \mu m$ Technology.
+\subsection{Orientation}
-This Testwafer should contain almost all test structures to evaulate and qualify the technology-depended paramters. So on Wafer we placed structures to measure the sheet-resistance of all Poly- and Metallayer, as well capacitors, NMOS and PMOS transistors, bipolar junction transistors, diodes and flash cells. There are even gate cells like NAND3, NOR3 and some others used for ring oscillators.
+There are two different systems to give orientation while talking about locations on the die.
+One system use words like Top (= upper side), Right, Bottom (= lower side) and Left.
+The other system uses cardinal directions like North, East, South and West to name the same.
+Both systems are very common, here the cardinal directions are prefered, just as convention.
-The parameter, measured from all test structures are used for the Spice3f and other models.
+\input{picture-wafer_size.tex}
+Wafers smaller than 8 inches, or 200 mm, have a flat side to give orientation and encode the crystal structure (eg. \{100\}).
+In this document, the South side is the one with the flat.
-\subsection{Orientation}
+\subsection{Process Variation}
+
+All machines in the process flow affects the quality of wafer processing.
+This results in Variations, regarding the location of the test structure on the wafer as well as the structures itself.
-There are to different systems to give orientation while talking about locations on the die. One systems use words like top (= upper side), right, buttion (= lower side) and left. The other systems uses cardinal directions like north, east, south and west to name the same. Both systems are very common, but here we use the cardinal directions, just as convention.
+For instance etching is slightly more aggressiv on one side of a structure than on the opposite side.
+One aim of the Test Wafer is also to understand und measure this effects.
-Wafers smaller than 8 inches, or 200 mm, have a flat side to give orientation and encode the crystal structure. Well, we like to call the side South with the notch or the flats.
+Therefor the wafer is divided into many small, repetative pieces, called dies, to get quantified values for the location.
+It is possible to measure structures always at the same die location over and over for many wafers.
-All machines in the process flow has effects while dealing with the structures on the wafer. For instance etching is slightly more aggressiv on the eastern side of a structure than on the western side. To understand und measure this effects, all structures on the die are placed in a dedicated way. Structures are grouped together in a triangle. This triangle we call quarter, while placed four times on the same die, each rotated 90 degrees.
+Also, every die itself is build from four triangles (representing one side) of the same test structures to measure how the process works from different directions.
+This means, that all structures are grouped together in four triangles, each rotated by 90 degrees, forming a square.
-\input{principle_quarter.tex}
+\input{principle-quarter.tex}
+
+Quantifying the test structures, the location can be referenced by the die position and the quarter (North, East, South and West) on die where the test structures is measured.
+There is no recommandations about the metrics for the location.
\subsection{Four-terminal Sensing}
-\input{schematic_4terminal.tex}
-\input{principle_rsquare.tex}
+The prefered measurement method for the test structures is the so-calld Four-terminal Sensing, or Kelvin sensing.
+This is an electrical impedance measuring technique that uses pairs of current-carrying and voltage-sensing probes to make accurate measurements.
+
+Four-terminal Sensing has advantage for precise measurement of low resistance values by eliminationg the lead and contact resistance for the measurement.
+Therefor almost all test structures here using four contact pads to place the probes on them.
+
+\input{schematic-4terminal.tex}
+
+Best results are given, when the sense wire probes are placed close to device-under-test (DUT) as the inside pair, while the force wire probes are the outside pair.
+Otherwise the accuracy can be affected, because more of the lead is included in the measurement.
+
+It is also recommended that every measurement starts with very low current, while voltages could break the test structures.
+The current respects the total resistance on the path and results in a voltage which can be measured on the sensing wire probes.
+Regarding Ohm's law
+
+\begin{equation}\label{1}
+ Resistance = \frac{Voltage}{Current}
+\end{equation}
+
+the Resistance can be calculated by driven Current and resulting Voltage.
+
+
+\input{principle-rsquare.tex}
\clearpage
diff --git a/Documents/LaTeX/picture-wafer_size.tex b/Documents/LaTeX/picture-wafer_size.tex
new file mode 100644
index 0000000000000000000000000000000000000000..090b1f58e7a11b1b2d22d7e0a5cedae7d9e0ceb6
--- /dev/null
+++ b/Documents/LaTeX/picture-wafer_size.tex
@@ -0,0 +1,51 @@
+%% ************ LibreSilicon's 1st TestWafer *******************
+%%
+%% Organisation: Chipforge
+%% Germany / European Union
+%%
+%% Profile: Chipforge focus on fine System-on-Chip Cores in
+%% Verilog HDL Code which are easy understandable and
+%% adjustable. For further information see
+%% www.chipforge.org
+%% there are projects from small cores up to PCBs, too.
+%%
+%% File: PearlRiver/Documents/LaTeX/picture_wafer_size.tex
+%%
+%% Purpose: Picture for Wafer Size compare and Flats
+%%
+%% ************ LaTeX with circdia.sty package ***************
+%%
+%% ///////////////////////////////////////////////////////////////////
+%%
+%% Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
+%% All rights reserved.
+%%
+%% This Standard Cell Library is licensed under the Libre Silicon
+%% public license; you can redistribute it and/or modify it under
+%% the terms of the Libre Silicon public license as published by
+%% the Libre Silicon alliance, either version 1 of the License, or
+%% (at your option) any later version.
+%%
+%% This design is distributed in the hope that it will be useful,
+%% but WITHOUT ANY WARRANTY; without even the implied warranty of
+%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+%% See the Libre Silicon Public License for more details.
+%%
+%% ///////////////////////////////////////////////////////////////////
+\begin{center}
+ Picture - Wafer Size and Flats
+ \begin{figure}[h]
+ \begin{center}
+ \begin{tikzpicture}[]
+ \draw (0,0) arc (-60:240:5);
+ \draw (0,0) arc (-60:240:6.12);
+ \draw (0,0) arc (-60:240:7.5);
+ \draw (0,0) -- (-7.5,0);
+ \node at (-2,8) {4-inch Wafer};
+ \node at (-2.5,10.5) {5-inch Wafer};
+ \node at (-3,13) {6-inch Wafer};
+ \node at (-3.5,-0.5) {flats on South};
+ \end{tikzpicture}
+ \end{center}
+ \end{figure}
+\end{center}
diff --git a/Documents/LaTeX/principle_quarter.tex b/Documents/LaTeX/principle-quarter.tex
similarity index 91%
rename from Documents/LaTeX/principle_quarter.tex
rename to Documents/LaTeX/principle-quarter.tex
index 9748cad2da279c59a9ea70d812d8524e5b41e386..365dc7182a3e4cf987e51adc4c7ebac2f591bcff 100644
--- a/Documents/LaTeX/principle_quarter.tex
+++ b/Documents/LaTeX/principle-quarter.tex
@@ -33,7 +33,7 @@
%%
%% ///////////////////////////////////////////////////////////////////
\begin{center}
- One Die with all Quarters
+ Principle - One Die with all Quarters
\begin{figure}[h]
\begin{center}
\begin{tikzpicture}[]
@@ -42,6 +42,10 @@
\draw (7,0.5) -- (7,6.5) -- (4,3.5) -- cycle;
\draw (6.5,7) -- (0.5,7) -- (3.5,4) -- cycle;
\draw (0,6.5) -- (0,0.5) -- (3,3.5) -- cycle;
+ \node at (6,3.5) {East};
+ \node at (3.5,6) {North};
+ \node at (1,3.5) {West};
+ \node at (3.5,1) {South};
\end{tikzpicture}
\end{center}
\end{figure}
diff --git a/Documents/LaTeX/principle-rsquare.tex b/Documents/LaTeX/principle-rsquare.tex
new file mode 100644
index 0000000000000000000000000000000000000000..d0bc07e62e9834da3d58019cc99042ac4b4b6913
--- /dev/null
+++ b/Documents/LaTeX/principle-rsquare.tex
@@ -0,0 +1,57 @@
+%% ************ LibreSilicon's 1st TestWafer *******************
+%%
+%% Organisation: Chipforge
+%% Germany / European Union
+%%
+%% Profile: Chipforge focus on fine System-on-Chip Cores in
+%% Verilog HDL Code which are easy understandable and
+%% adjustable. For further information see
+%% www.chipforge.org
+%% there are projects from small cores up to PCBs, too.
+%%
+%% File: PearlRiver/Documents/LaTeX/die_quarter.tex
+%%
+%% Purpose: Principle Description Pictgure for quarters
+%%
+%% ************ LaTeX with circdia.sty package ***************
+%%
+%% ///////////////////////////////////////////////////////////////////
+%%
+%% Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
+%% All rights reserved.
+%%
+%% This Standard Cell Library is licensed under the Libre Silicon
+%% public license; you can redistribute it and/or modify it under
+%% the terms of the Libre Silicon public license as published by
+%% the Libre Silicon alliance, either version 1 of the License, or
+%% (at your option) any later version.
+%%
+%% This design is distributed in the hope that it will be useful,
+%% but WITHOUT ANY WARRANTY; without even the implied warranty of
+%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+%% See the Libre Silicon Public License for more details.
+%%
+%% ///////////////////////////////////////////////////////////////////
+\begin{center}
+ Principle - $R_\square$
+ \begin{figure}[h]
+ \begin{center}
+ \begin{tikzpicture}[]
+ \draw[thick] (0,0) -- (4,0) -- (4,1) -- (0,1) -- cycle; % front
+ \draw[thick] (0,1) -- (2,3) -- (6,3) -- (4,1) -- cycle; % 1st top
+ \draw[thick] (4,0) -- (4,1) -- (6,3) -- (6,2) -- cycle; % 1st boarder
+ \draw[thick] (2,3) -- (4,5) -- (8,5) -- (6,3) -- cycle; % 2nd top
+ \draw[thick] (6,3) -- (8,5) -- (8,4) -- (6,2) -- cycle; % 2nd boarder
+ % width
+ \node at (2,-0.75) {w};
+ \draw[|<->|] (0,-1) -- (4,-1);
+ % length
+ \node at (6.9,2) {l};
+ \draw[|<->|] (5,-0.3) -- (9,3.7);
+ % hight
+ \node at (8.75,4.5) {h};
+ \draw[|<->|] (9,4) -- (9,5);
+ \end{tikzpicture}
+ \end{center}
+ \end{figure}
+\end{center}
diff --git a/Documents/LaTeX/schematic_4terminal.tex b/Documents/LaTeX/schematic-4terminal.tex
similarity index 80%
rename from Documents/LaTeX/schematic_4terminal.tex
rename to Documents/LaTeX/schematic-4terminal.tex
index bf8d4dfd2f1acfabcb1f87a5d34d2a024ffe2479..737d3bb819b60348c7389ccade09404f5a354bad 100644
--- a/Documents/LaTeX/schematic_4terminal.tex
+++ b/Documents/LaTeX/schematic-4terminal.tex
@@ -33,10 +33,10 @@
%%
%% ///////////////////////////////////////////////////////////////////
\begin{center}
- Schematic (Four-terminal Sensing)
+ Four-terminal Sensing with instrument, probes and device-under-test
\begin{figure}[h]
\begin{center}
- \begin{circuitdiagram}{32}{25}
+ \begin{circuitdiagram}{42}{25}
% current source with ground
\ground{3}{0}{D}
\wire{3}{1}{3}{8}
@@ -68,20 +68,24 @@
\wire{15}{6}{24}{6}
\Voltarrow{25}{16}{25}{6}{r}{U}
% device under test
- \resis{31}{11}{V}{device-under-test}{}
- \wire{26}{1}{30.5}{1}
- \pin{31}{1}{Dr}{I-}
- \wire{26}{6}{30.5}{6}
- \pin{31}{6}{UD}{U-}
- \wire{26}{16}{30.5}{16}
- \pin{31}{16}{UD}{U+}
- \wire{26}{21}{30.5}{21}
- \pin{31}{21}{Ur}{I+}
+ \resis{40}{11}{V}{DUT}{}
+ \wire{26}{1}{35.5}{1}
+ \pin{40}{1}{Dr}{}
+ \power{35}{1}{R}{I-}
+ \wire{26}{6}{35.5}{6}
+ \pin{40}{6}{UD}{}
+ \power{35}{6}{R}{U-}
+ \wire{26}{16}{35.5}{16}
+ \pin{40}{16}{UD}{}
+ \power{35}{16}{R}{U+}
+ \wire{26}{21}{35.5}{21}
+ \pin{40}{21}{Ur}{}
+ \power{35}{21}{R}{I+}
%
- \wire{31}{2}{31}{5}
- \wire{31}{7}{31}{8}
- \wire{31}{14}{31}{15}
- \wire{31}{17}{31}{20}
+ \wire{40}{2}{40}{5}
+ \wire{40}{7}{40}{8}
+ \wire{40}{14}{40}{15}
+ \wire{40}{17}{40}{20}
\end{circuitdiagram}
\end{center}
\end{figure}
diff --git a/Documents/LaTeX/schematic_invring.tex b/Documents/LaTeX/schematic-invring.tex
similarity index 56%
rename from Documents/LaTeX/schematic_invring.tex
rename to Documents/LaTeX/schematic-invring.tex
index 33b8f436a48a07d5da8034bd1af2ebdab7aef361..7d8e8a23d7741baf198b7bf3584bbed21605c751 100644
--- a/Documents/LaTeX/schematic_invring.tex
+++ b/Documents/LaTeX/schematic-invring.tex
@@ -36,24 +36,33 @@
Schematic (Ring Oscillator with INV-Gates)
\begin{figure}[h]
\begin{center}
- \begin{circuitdiagram}{60}{9}
- \pin{1}{7}{L}{EN} % pin EN, enable oscillation
- \pin{59}{5}{R}{$f_{INV}$} % pin FINV,
- \gate[\inputs{2}]{nand}{5}{5}{R}{}{} % NAND gate -> right
- \wire{9}{5}{12}{5} % interconnect wire
- \gate{not}{15}{5}{R}{}{} % INV gate -> right
- \wire{18}{5}{22}{5} % interconnect wire
- \gate{not}{25}{5}{R}{}{} % INV gate -> right
- \wire{28}{5}{32}{5} % interconnect wire
- \gate{not}{35}{5}{R}{}{} % INV gate -> right
- \wire{38}{5}{42}{5} % interconnect wire
- \gate{not}{45}{5}{R}{}{} % INV gate -> right
- \wire{48}{5}{52}{5} % interconnect wire
- \gate{not}{55}{5}{R}{}{} % INV gate -> right
- \junct{51}{5}
- \wire{51}{5}{51}{1} % feedback wire
- \wire{2}{1}{51}{1} % interconnect wire
- \wire{2}{1}{2}{3} % feedback wire
+ \begin{circuitdiagram}{60}{14}
+ \pin{1}{12}{L}{EN} % pin EN, enable oscillation
+ \pin{59}{10}{R}{$f_{INV}$} % pin FINV,
+ \gate[\inputs{2}]{nand}{5}{10}{R}{}{} % NAND gate -> right
+ \wire{9}{10}{12}{10} % interconnect wire
+ \gate{not}{15}{10}{R}{}{} % INV gate -> right
+ \wire{18}{10}{22}{10} % interconnect wire
+ \gate{not}{25}{10}{R}{}{} % INV gate -> right
+ \wire{28}{10}{32}{10} % interconnect wire
+ \gate{not}{35}{10}{R}{}{} % INV gate -> right
+ \wire{38}{10}{42}{10} % interconnect wire
+ \gate{not}{45}{10}{R}{}{} % INV gate -> right
+ \wire{48}{10}{52}{10} % interconnect wire
+ \gate{not}{55}{10}{R}{}{} % INV gate -> right
+ \junct{51}{10}
+ \wire{51}{10}{51}{4}
+ \gate{not}{55}{10}{R}{}{} % INV gate -> right
+ \wire{51}{4}{48}{4}
+ \gate{not}{46}{4}{L}{}{} % INV gate <- left
+ \wire{39}{4}{43}{4}
+ \gate{not}{36}{4}{L}{}{} % INV gate <- left
+ \wire{29}{4}{33}{4}
+ \gate{not}{26}{4}{L}{}{} % INV gate <- left
+ \wire{19}{4}{23}{4}
+ \gate{not}{16}{4}{L}{}{} % INV gate <- left
+ \wire{2}{4}{13}{4}
+ \wire{2}{4}{2}{8}
\end{circuitdiagram}
\end{center}
\end{figure}
diff --git a/Documents/LaTeX/schematic-nand3ring.tex b/Documents/LaTeX/schematic-nand3ring.tex
new file mode 100644
index 0000000000000000000000000000000000000000..db8c0e34db7536e8ced230ab797d20830795ec68
--- /dev/null
+++ b/Documents/LaTeX/schematic-nand3ring.tex
@@ -0,0 +1,84 @@
+%% ************ LibreSilicon's 1st TestWafer *******************
+%%
+%% Organisation: Chipforge
+%% Germany / European Union
+%%
+%% Profile: Chipforge focus on fine System-on-Chip Cores in
+%% Verilog HDL Code which are easy understandable and
+%% adjustable. For further information see
+%% www.chipforge.org
+%% there are projects from small cores up to PCBs, too.
+%%
+%% File: PearlRiver/Documents/LaTeX/schematic_nand3ring.tex
+%%
+%% Purpose: Schematic File for Ring Oscillator with NAND3-Gates
+%%
+%% ************ LaTeX with circdia.sty package ***************
+%%
+%% ///////////////////////////////////////////////////////////////////
+%%
+%% Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
+%% All rights reserved.
+%%
+%% This Standard Cell Library is licensed under the Libre Silicon
+%% public license; you can redistribute it and/or modify it under
+%% the terms of the Libre Silicon public license as published by
+%% the Libre Silicon alliance, either version 1 of the License, or
+%% (at your option) any later version.
+%%
+%% This design is distributed in the hope that it will be useful,
+%% but WITHOUT ANY WARRANTY; without even the implied warranty of
+%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+%% See the Libre Silicon Public License for more details.
+%%
+%% ///////////////////////////////////////////////////////////////////
+\begin{center}
+ Schematic (Ring Oscillator with NAND3-Gates)
+ \begin{figure}[h]
+ \begin{center}
+ \begin{circuitdiagram}{60}{14}
+ \pin{1}{12}{L}{EN} % pin EN, enable oscillation
+ \pin{59}{10}{R}{$f_{NAND}$} % pin FNAND,
+ \gate[\inputs{2}]{nand}{5}{10}{R}{}{} % NAND gate -> right
+ \wire{9}{10}{12}{10} % interconnect wire
+ \wire{12}{8}{12}{12} % gate shortage
+ \junct{12}{10}
+ \gate[\inputs{3}]{nand}{15}{10}{R}{}{} % NAND gate -> right
+ \wire{19}{10}{22}{10} % interconnect wire
+ \wire{22}{8}{22}{12} % gate shortage
+ \junct{22}{10}
+ \gate[\inputs{3}]{nand}{25}{10}{R}{}{} % NAND gate -> right
+ \wire{29}{10}{32}{10} % interconnect wire
+ \wire{32}{8}{32}{12} % gate shortage
+ \junct{32}{10}
+ \gate[\inputs{3}]{nand}{35}{10}{R}{}{} % NAND gate -> right
+ \wire{39}{10}{42}{10} % interconnect wire
+ \wire{42}{8}{42}{12} % gate shortage
+ \junct{42}{10}
+ \gate[\inputs{3}]{nand}{45}{10}{R}{}{} % NAND gate -> right
+ \wire{49}{10}{52}{10} % interconnect wire
+ \gate{not}{55}{10}{R}{}{} % INV gate -> right
+ \junct{51}{10}
+ \wire{51}{10}{51}{4} % feedback wire
+ \wire{2}{4}{12}{4} % interconnect wire
+ \wire{2}{4}{2}{8} % feedback wire
+ \gate[\inputs{3}]{nand}{46}{4}{L}{}{} % NAND gate <- left
+ \wire{49}{2}{49}{6} % gate shortage
+ \junct{49}{4}
+ \wire{49}{4}{51}{4}
+ \wire{39}{4}{42}{4}
+ \gate[\inputs{3}]{nand}{36}{4}{L}{}{} % NAND gate <- left
+ \wire{39}{2}{39}{6} % gate shortage
+ \junct{39}{4}
+ \wire{29}{4}{32}{4} % interconnect wire
+ \gate[\inputs{3}]{nand}{26}{4}{L}{}{} % NAND gate <- left
+ \wire{29}{2}{29}{6} % gate shortage
+ \junct{29}{4}
+ \wire{19}{4}{22}{4} % interconnect wire
+ \gate[\inputs{3}]{nand}{16}{4}{L}{}{} % NAND gate <- left
+ \wire{19}{2}{19}{6} % gate shortage
+ \junct{19}{4}
+ \end{circuitdiagram}
+ \end{center}
+ \end{figure}
+\end{center}
diff --git a/Documents/LaTeX/schematic-nor3ring.tex b/Documents/LaTeX/schematic-nor3ring.tex
new file mode 100644
index 0000000000000000000000000000000000000000..c5866b46d7cf65b2ea7af37beb2873aecd0bd8d4
--- /dev/null
+++ b/Documents/LaTeX/schematic-nor3ring.tex
@@ -0,0 +1,84 @@
+%% ************ LibreSilicon's 1st TestWafer *******************
+%%
+%% Organisation: Chipforge
+%% Germany / European Union
+%%
+%% Profile: Chipforge focus on fine System-on-Chip Cores in
+%% Verilog HDL Code which are easy understandable and
+%% adjustable. For further information see
+%% www.chipforge.org
+%% there are projects from small cores up to PCBs, too.
+%%
+%% File: PearlRiver/Documents/LaTeX/schematic_nor3ring.tex
+%%
+%% Purpose: Schematic File for Ring Oscillator with NOR3-Gates
+%%
+%% ************ LaTeX with circdia.sty package ***************
+%%
+%% ///////////////////////////////////////////////////////////////////
+%%
+%% Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
+%% All rights reserved.
+%%
+%% This Standard Cell Library is licensed under the Libre Silicon
+%% public license; you can redistribute it and/or modify it under
+%% the terms of the Libre Silicon public license as published by
+%% the Libre Silicon alliance, either version 1 of the License, or
+%% (at your option) any later version.
+%%
+%% This design is distributed in the hope that it will be useful,
+%% but WITHOUT ANY WARRANTY; without even the implied warranty of
+%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+%% See the Libre Silicon Public License for more details.
+%%
+%% ///////////////////////////////////////////////////////////////////
+\begin{center}
+ Schematic (Ring Oscillator with NOR3-Gates)
+ \begin{figure}[h]
+ \begin{center}
+ \begin{circuitdiagram}{60}{14}
+ \pin{1}{12}{L}{$\overline{EN}$} % pin EN, enable oscillation
+ \pin{59}{10}{R}{$f_{NOR}$} % pin FNOR,
+ \gate[\inputs{2}]{nor}{5}{10}{R}{}{} % NOR gate -> right
+ \wire{9}{10}{12}{10} % interconnect wire
+ \wire{12}{8}{12}{12} % gate shortage
+ \junct{12}{10}
+ \gate[\inputs{3}]{nor}{15}{10}{R}{}{} % NOR gate -> right
+ \wire{19}{10}{22}{10} % interconnect wire
+ \wire{22}{8}{22}{12} % gate shortage
+ \junct{22}{10}
+ \gate[\inputs{3}]{nor}{25}{10}{R}{}{} % NOR gate -> right
+ \wire{29}{10}{32}{10} % interconnect wire
+ \wire{32}{8}{32}{12} % gate shortage
+ \junct{32}{10}
+ \gate[\inputs{3}]{nor}{35}{10}{R}{}{} % NOR gate -> right
+ \wire{39}{10}{42}{10} % interconnect wire
+ \wire{42}{8}{42}{12} % gate shortage
+ \junct{42}{10}
+ \gate[\inputs{3}]{nor}{45}{10}{R}{}{} % NOR gate -> right
+ \wire{49}{10}{52}{10} % interconnect wire
+ \gate{not}{55}{10}{R}{}{} % INV gate -> right
+ \junct{51}{10}
+ \wire{51}{10}{51}{4} % feedback wire
+ \wire{2}{4}{12}{4} % interconnect wire
+ \wire{2}{4}{2}{8} % feedback wire
+ \gate[\inputs{3}]{nor}{46}{4}{L}{}{} % NOR gate <- left
+ \wire{49}{2}{49}{6} % gate shortage
+ \junct{49}{4}
+ \wire{49}{4}{51}{4}
+ \wire{39}{4}{42}{4}
+ \gate[\inputs{3}]{nor}{36}{4}{L}{}{} % NOR gate <- left
+ \wire{39}{2}{39}{6} % gate shortage
+ \junct{39}{4}
+ \wire{29}{4}{32}{4} % interconnect wire
+ \gate[\inputs{3}]{nor}{26}{4}{L}{}{} % NOR gate <- left
+ \wire{29}{2}{29}{6} % gate shortage
+ \junct{29}{4}
+ \wire{19}{4}{22}{4} % interconnect wire
+ \gate[\inputs{3}]{nor}{16}{4}{L}{}{} % NOR gate <- left
+ \wire{19}{2}{19}{6} % gate shortage
+ \junct{19}{4}
+ \end{circuitdiagram}
+ \end{center}
+ \end{figure}
+\end{center}
diff --git a/Documents/LaTeX/schematic_nand3ring.tex b/Documents/LaTeX/schematic_nand3ring.tex
deleted file mode 100644
index f4ec6c39a2a6c5c769a4e68e12b5e820ad5a44fa..0000000000000000000000000000000000000000
--- a/Documents/LaTeX/schematic_nand3ring.tex
+++ /dev/null
@@ -1,68 +0,0 @@
-%% ************ LibreSilicon's 1st TestWafer *******************
-%%
-%% Organisation: Chipforge
-%% Germany / European Union
-%%
-%% Profile: Chipforge focus on fine System-on-Chip Cores in
-%% Verilog HDL Code which are easy understandable and
-%% adjustable. For further information see
-%% www.chipforge.org
-%% there are projects from small cores up to PCBs, too.
-%%
-%% File: PearlRiver/Documents/LaTeX/schematic_nand3ring.tex
-%%
-%% Purpose: Schematic File for Ring Oscillator with NAND3-Gates
-%%
-%% ************ LaTeX with circdia.sty package ***************
-%%
-%% ///////////////////////////////////////////////////////////////////
-%%
-%% Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
-%% All rights reserved.
-%%
-%% This Standard Cell Library is licensed under the Libre Silicon
-%% public license; you can redistribute it and/or modify it under
-%% the terms of the Libre Silicon public license as published by
-%% the Libre Silicon alliance, either version 1 of the License, or
-%% (at your option) any later version.
-%%
-%% This design is distributed in the hope that it will be useful,
-%% but WITHOUT ANY WARRANTY; without even the implied warranty of
-%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-%% See the Libre Silicon Public License for more details.
-%%
-%% ///////////////////////////////////////////////////////////////////
-\begin{center}
- Schematic (Ring Oscillator with NAND3-Gates)
- \begin{figure}[h]
- \begin{center}
- \begin{circuitdiagram}{60}{9}
- \pin{1}{7}{L}{EN} % pin EN, enable oscillation
- \pin{59}{5}{R}{$f_{NAND}$} % pin FNAND,
- \gate[\inputs{2}]{nand}{5}{5}{R}{}{} % NAND gate -> right
- \wire{9}{5}{12}{5} % interconnect wire
- \wire{12}{3}{12}{7} % gate shortage
- \junct{12}{5}
- \gate[\inputs{3}]{nand}{15}{5}{R}{}{} % NAND gate -> right
- \wire{19}{5}{22}{5} % interconnect wire
- \wire{22}{3}{22}{7} % gate shortage
- \junct{22}{5}
- \gate[\inputs{3}]{nand}{25}{5}{R}{}{} % NAND gate -> right
- \wire{29}{5}{32}{5} % interconnect wire
- \wire{32}{3}{32}{7} % gate shortage
- \junct{32}{5}
- \gate[\inputs{3}]{nand}{35}{5}{R}{}{} % NAND gate -> right
- \wire{39}{5}{42}{5} % interconnect wire
- \wire{42}{3}{42}{7} % gate shortage
- \junct{42}{5}
- \gate[\inputs{3}]{nand}{45}{5}{R}{}{} % NAND gate -> right
- \wire{49}{5}{52}{5} % interconnect wire
- \gate{not}{55}{5}{R}{}{} % INV gate -> right
- \junct{51}{5}
- \wire{51}{5}{51}{1} % feedback wire
- \wire{2}{1}{51}{1} % interconnect wire
- \wire{2}{1}{2}{3} % feedback wire
- \end{circuitdiagram}
- \end{center}
- \end{figure}
-\end{center}
diff --git a/Documents/LaTeX/schematic_nor3ring.tex b/Documents/LaTeX/schematic_nor3ring.tex
deleted file mode 100644
index 650cac029e8ec36aeba6f5662e2f2c3b2e93f5fa..0000000000000000000000000000000000000000
--- a/Documents/LaTeX/schematic_nor3ring.tex
+++ /dev/null
@@ -1,68 +0,0 @@
-%% ************ LibreSilicon's 1st TestWafer *******************
-%%
-%% Organisation: Chipforge
-%% Germany / European Union
-%%
-%% Profile: Chipforge focus on fine System-on-Chip Cores in
-%% Verilog HDL Code which are easy understandable and
-%% adjustable. For further information see
-%% www.chipforge.org
-%% there are projects from small cores up to PCBs, too.
-%%
-%% File: PearlRiver/Documents/LaTeX/schematic_nor3ring.tex
-%%
-%% Purpose: Schematic File for Ring Oscillator with NOR3-Gates
-%%
-%% ************ LaTeX with circdia.sty package ***************
-%%
-%% ///////////////////////////////////////////////////////////////////
-%%
-%% Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
-%% All rights reserved.
-%%
-%% This Standard Cell Library is licensed under the Libre Silicon
-%% public license; you can redistribute it and/or modify it under
-%% the terms of the Libre Silicon public license as published by
-%% the Libre Silicon alliance, either version 1 of the License, or
-%% (at your option) any later version.
-%%
-%% This design is distributed in the hope that it will be useful,
-%% but WITHOUT ANY WARRANTY; without even the implied warranty of
-%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-%% See the Libre Silicon Public License for more details.
-%%
-%% ///////////////////////////////////////////////////////////////////
-\begin{center}
- Schematic (Ring Oscillator with NOR3-Gates)
- \begin{figure}[h]
- \begin{center}
- \begin{circuitdiagram}{60}{9}
- \pin{1}{7}{L}{$\overline{EN}$} % pin EN, enable oscillation
- \pin{59}{5}{R}{$f_{NOR}$} % pin FNOR,
- \gate[\inputs{2}]{nor}{5}{5}{R}{}{} % NOR gate -> right
- \wire{9}{5}{12}{5} % interconnect wire
- \wire{12}{3}{12}{7} % gate shortage
- \junct{12}{5}
- \gate[\inputs{3}]{nor}{15}{5}{R}{}{} % NOR gate -> right
- \wire{19}{5}{22}{5} % interconnect wire
- \wire{22}{3}{22}{7} % gate shortage
- \junct{22}{5}
- \gate[\inputs{3}]{nor}{25}{5}{R}{}{} % NOR gate -> right
- \wire{29}{5}{32}{5} % interconnect wire
- \wire{32}{3}{32}{7} % gate shortage
- \junct{32}{5}
- \gate[\inputs{3}]{nor}{35}{5}{R}{}{} % NOR gate -> right
- \wire{39}{5}{42}{5} % interconnect wire
- \wire{42}{3}{42}{7} % gate shortage
- \junct{42}{5}
- \gate[\inputs{3}]{nor}{45}{5}{R}{}{} % NOR gate -> right
- \wire{49}{5}{52}{5} % interconnect wire
- \gate{not}{55}{5}{R}{}{} % INV gate -> right
- \junct{51}{5}
- \wire{51}{5}{51}{1} % feedback wire
- \wire{2}{1}{51}{1} % interconnect wire
- \wire{2}{1}{2}{3} % feedback wire
- \end{circuitdiagram}
- \end{center}
- \end{figure}
-\end{center}
diff --git a/Documents/LaTeX/teststructures.tex b/Documents/LaTeX/teststructures.tex
new file mode 100644
index 0000000000000000000000000000000000000000..4e421deda54ce8dfebe89b5e27d804ee00f69ca7
--- /dev/null
+++ b/Documents/LaTeX/teststructures.tex
@@ -0,0 +1,64 @@
+%% ************ LibreSilicon's 1st TestWafer *******************
+%%
+%% Organisation: Chipforge
+%% Germany / European Union
+%%
+%% Profile: Chipforge focus on fine System-on-Chip Cores in
+%% Verilog HDL Code which are easy understandable and
+%% adjustable. For further information see
+%% www.chipforge.org
+%% there are projects from small cores up to PCBs, too.
+%%
+%% File: PearlRiver/Documents/LaTeX/teststructures.tex
+%%
+%% Purpose: Chapter File for Test Structures
+%%
+%% ************ LaTeX with circdia.sty package ***************
+%%
+%% ///////////////////////////////////////////////////////////////////
+%%
+%% Copyright (c) 2018 by chipforge <hsank@nospam.chipforge.org>
+%% All rights reserved.
+%%
+%% This Standard Cell Library is licensed under the Libre Silicon
+%% public license; you can redistribute it and/or modify it under
+%% the terms of the Libre Silicon public license as published by
+%% the Libre Silicon alliance, either version 1 of the License, or
+%% (at your option) any later version.
+%%
+%% This design is distributed in the hope that it will be useful,
+%% but WITHOUT ANY WARRANTY; without even the implied warranty of
+%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+%% See the Libre Silicon Public License for more details.
+%%
+%% ///////////////////////////////////////////////////////////////////
+\section{Test Structures}
+
+\subsection{Metall and Poly Resistance}
+
+% wells
+% stripes
+% pad
+
+\subsection{Contact and Via Resistance}
+
+\subsection{Layer Capacitance}
+
+\subsection{Diodes}
+
+% parasitic diodes, Zener diodes
+
+\subsection{p-channel and n-channels Transistors}
+
+% p-/n- Tables
+
+\subsection{Bipolar Junctions Transistors}
+
+\subsection{Experimental}
+
+% High-Voltage Fets
+% SONOS
+
+\subsection{Ring Oscillators}
+
+\clearpage
diff --git a/Documents/PearlRiver.pdf b/Documents/PearlRiver.pdf
index b9bffa2559414672567dc9b77c06dd5c0de4a164..bb1189c259232e620923636bb5a1cb0987cc7d68 100644
Binary files a/Documents/PearlRiver.pdf and b/Documents/PearlRiver.pdf differ
diff --git a/GNUmakefile b/GNUmakefile
index 16b2d0dc3069516af2e9d9f0a37038fc42e7b450..fbf06f9ca2b653ad144fb410119d9fcb479529cc 100644
--- a/GNUmakefile
+++ b/GNUmakefile
@@ -54,7 +54,7 @@ DATE := $(shell date +%Y%m%d)
# project tools
-LATEX ?= pdflatex -output-directory $(DOCUMENTSDIR) $(OUTPUTDIR)
+# ??
# default
@@ -96,13 +96,14 @@ dist: clean
.PHONY: clean
clean:
$(ECHO) "---- clean up all intermediate files ----"
- $(MAKE) -C $(DOCUMENTSDIR)/LaTeX -f build.mk $@
+ $(MAKE) -C $(DOCUMENTSDIR)/LaTeX -f GNUmakefile $@
# ----------------------------------------------------------------
# DOCUMENTATION TARGETS
# ----------------------------------------------------------------
.PHONY: doc
-doc: $(DOCUMENTSDIR)/LaTeX/$(PROJECT).tex $(DOCUMENTSDIR)/LaTeX/revision.tex
- TEXINPUTS=$$TEXINPUT:./$(DOCUMENTSDIR)/LaTeX $(LATEX) $(<F)
-# TEXINPUTS=::../../circdia xelatex PearlRiver.tex
+doc:
+ $(MAKE) -C $(DOCUMENTSDIR)/LaTeX -f GNUmakefile $@
+
+
diff --git a/README.md b/README.md
index 9b960211902c3000868b8452556e8c560bd1df74..92ac750858ffa191e711e4b65f6a08be90052b38 100644
--- a/README.md
+++ b/README.md
@@ -36,13 +36,23 @@ for the whole die.
For documentation we are using LaTeX.
-All LaTeX files are stored inside
+All original LaTeX files are stored inside
* Documentation/LaTeX Folder
-Please read the documentation carefully.
+You can build the documentation out of the LaTeX sources just by using the Makefile
-If you do not understand, what the hack we are doing here, please sit back with a good textbook about CMOS or ASIC technology development and learn. Please come back later.
+```
+make doc
+```
+
+on top of the project directory.
+Please read the documentation with the PDF Viewer of your choise
-This branch was created to add the high-voltage NMOS device.
+```
+$PDFVIEWER Documentation/PearlRiver.pdf
+```
+carefully.
+
+If you do not understand, what the hack we are doing here, please sit back with a good textbook about CMOS or ASIC technology development and learn. Please come back later.