diff --git a/process_steps/process_hightech/process_hightech_contact.tex b/process_steps/process_hightech/process_hightech_contact.tex
index ffc12f547663e2477f83ff290104d1a86706212e..ba5c2639c5bbcb03fe37bc0256dd3a46042fe92d 100644
--- a/process_steps/process_hightech/process_hightech_contact.tex
+++ b/process_steps/process_hightech/process_hightech_contact.tex
@@ -12,8 +12,11 @@ These vias are in the fringe between front-end and back-end process.
\label{contact_cross_section}
\end{figure}
-As can be seen in \autoref{contact_cross_section}, the goal of this step is purely to deposit a layer of isolation oxide,
-get the holes into it, down to the silicide and polyside in order to form wires later on.
+In \autoref{chapter_silicide_and_cmp} we have already prepared the CMPed LTO which gives a well planarized oxide surface to
+etch through.
+
+As can be seen in \autoref{contact_cross_section}, the goal of this step is purely get the holes into it,
+down to the silicide and polyside in order to form wires later on.
We do not wanna etch down anywhere else than the silicide/polycide areas because these function as etch stoppers,
while everywhere else we might etch further than desired with small variations in etching time which might result
diff --git a/process_steps/process_hightech/process_hightech_interconnect.tex b/process_steps/process_hightech/process_hightech_interconnect.tex
index b2bc9a4b0d03e1e11d44c27a83402b58b1a5d522..da5e6d07258bc46ef4e163db94d874634f508d69 100644
--- a/process_steps/process_hightech/process_hightech_interconnect.tex
+++ b/process_steps/process_hightech/process_hightech_interconnect.tex
@@ -16,7 +16,7 @@ From here on it's basically just always the same game:
\item Deposit roughly 100nm LTO
\item Deposit 100nm nitride for CMP end stop
\item Deposit roughly 1\um LTO
- \item CMP away 600nm oxide (regulated by CMP end stop)
+ \item CMP away 200nm oxide (regulated by CMP end stop)
\item Etch vias
\item Sputter metal
\item Etch wires
diff --git a/process_steps/process_hightech/process_hightech_silicification.tex b/process_steps/process_hightech/process_hightech_silicification.tex
index 359ef0964f88c6a8c00be485a081bfc23238167a..9098852df3663a33f4b4571e0f197e81980b0eed 100644
--- a/process_steps/process_hightech/process_hightech_silicification.tex
+++ b/process_steps/process_hightech/process_hightech_silicification.tex
@@ -50,8 +50,6 @@ Considering, due to the edge effects during dry etching, the thickness of the ni
The deposition rates might variate between LPCVDs and recipes. It's at the discretion of the operation engineer to achieve those 50nm.
-\newpage
-
\subsection{Spacer etching}
Now we have to etch our nitride as anisotropic as possible.
@@ -74,6 +72,8 @@ Thit means the etching process only "sees" the sidewall as a "thicker layer" and
After that we will have our desired spacer geometry forming as well as any potentially resist covered area (if silicide block is being used) with sharp etches.
+\newpage
+
\subsection{Titanium deposition}
We deposit a layer of titanium with a thickness of around 30nm which will then be reacted into titanium-silicide and titanium-polycide respectively in the further steps.
@@ -116,8 +116,6 @@ The resulting $Ti Si_2$ film will be around 77nm in tickness with around 20nm un
A color change can be observed of the titanium on top of the oxide.
-\newpage
-
\subsection{Metal removal}
The unreacted titanium film on the dielectric layer such as $SiO_2$ or $SiN$ is selectively etched by APM (Ammonia and Hydrogen Peroxide Mixture) solution.
@@ -135,3 +133,35 @@ The unreacted titanium film on the dielectric layer such as $SiO_2$ or $SiN$ is
\end{figure}
After 2-3 minutes in APM, at room temperature, with a bit mechanical help, all the unreacted Titanium should be gone and the oxide should become visible again.
+
+\newpage
+
+\subsection{CMP}\label{chapter_silicide_and_cmp}
+
+After we formed all the active devices and added the silicide in order to reduce the sheet resistance of junctions and contacts we have to make sure that
+our devices will not be damaged during the planarization phase in order to contact through to them with the first metal layer.
+
+\begin{figure}[H]
+ \centering
+ \begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
+ \input{tikz_process_steps/silicification.cmp_stop.a.tex}
+ \end{tikzpicture}
+ \drawStepArrow{CMP endstop}
+ \begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
+ \input{tikz_process_steps/silicification.cmp_stop.b.tex}
+ \end{tikzpicture}
+ \drawStepArrow{CMP}
+ \begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
+ \input{tikz_process_steps/silicification.cmp_stop.c.tex}
+ \end{tikzpicture}
+ \caption{CMP, contact preparation}
+\end{figure}
+
+First we deposit around 100nm LTO as a pad oxide layer below the 100nm nitride, which serves as the CMP stop hard mask.
+Then we deposit 1\um LTO and CMP away the height differential of the active devices translated to the oxide.
+
+LTO was chosen because the silicide becomes unstable in the thermal ranges where phosphorus silicate glass becomes viscous enough
+for evening out the height differential by evening out by seeking its level during annealing.
+
+A thickness of 1\um of the LTO will make it more likely, that the dishing effect of the CMP pad causes devices to get damaged
+through an over consumption of the nitride hard mask.
diff --git a/process_steps/process_hightech/process_hightech_steps.pdf b/process_steps/process_hightech/process_hightech_steps.pdf
index e0ab4e96da9f4b913e81bc32e963056bc13615e7..0e2d6e5f9ea9cff9450c3562aab89cf72253153d 100644
Binary files a/process_steps/process_hightech/process_hightech_steps.pdf and b/process_steps/process_hightech/process_hightech_steps.pdf differ