diff --git a/process_steps/process_hightech/process_hightech_fox.tex b/process_steps/process_hightech/process_hightech_fox.tex
index 50230260612b733d8636e159766cef7516736b38..7d71b06d8546887ad7d6a1ea1a947191102f98e3 100644
--- a/process_steps/process_hightech/process_hightech_fox.tex
+++ b/process_steps/process_hightech/process_hightech_fox.tex
@@ -19,8 +19,6 @@ Only within the active areas we want to allow the poly layer to touch down close
The mask is called "fox" on the mask set.
-LTO is used here, but can also be replaced by PSG if LTO deposition isn't available for higher thicknesses.
-
The LTO thickness has been chosen to be 200nm which is thin enough for the polysilicon gates to overcome the height difference without damage and still being enough for eliminating parasitic effects.
\newpage
@@ -34,16 +32,16 @@ Now we need to deposit the silicon dioxide which will provide a spacer between t
\begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
\input{tikz_process_steps/fox.oxide_growth.a.tex}
\end{tikzpicture}
- \drawStepArrow{}
+ \drawStepArrow{CVD}
\begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
\input{tikz_process_steps/fox.oxide_growth.b.tex}
\end{tikzpicture}
- \caption{LTO/PSG deposition}
+ \caption{LTO deposition}
\end{figure}
-We deposit a roughly 200nm thick layer of LTO/PSG by putting the wafer into the LPCVD furnace.
+We deposit a roughly 200nm thick layer of LTO by putting the wafer into the LPCVD furnace.
-\subsection{Etching}\label{fox_etch}
+\subsection{FOX opening formation}\label{fox_etch}
We open the access to the silicon inside of the active areas in order to touch down with the polysilicon further on.
@@ -52,11 +50,16 @@ We open the access to the silicon inside of the active areas in order to touch d
\begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
\input{tikz_process_steps/fox.etching.a.tex}
\end{tikzpicture}
- \drawStepArrow{}
+ \drawStepArrow{Dry etch}
\begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
\input{tikz_process_steps/fox.etching.b.tex}
\end{tikzpicture}
- \caption{LTO/PSG etching}
+ \caption{LTO etching}
\end{figure}
The etching time variates from machine to machine and recipe to recipe. Do the math.
+
+After having etched through the LTO we have to make sure that the etching time goes up compared to the undensified LTO+nitride,
+which will be etched in \autoref{sonos_chapter}.
+For this reason, we put the wafer into the furnace and anneal the LTO for 30 minutes at 850\degreesC in inert atomsphere ($N_2$/$Ar$).
+
diff --git a/process_steps/process_hightech/process_hightech_gate.tex b/process_steps/process_hightech/process_hightech_gate.tex
index 8b89ae3554f9fe99e1027629654f6e597f128e02..ab5d8bd7f309b505504cbdd9ce2e256a09d19926 100644
--- a/process_steps/process_hightech/process_hightech_gate.tex
+++ b/process_steps/process_hightech/process_hightech_gate.tex
@@ -11,6 +11,9 @@ Now we have to build the initial gate structure which contains of the 40nm thick
The line spacing of the polysilicon electrode shape has to be at least 0.5\um because of the resolution of the stepper and also because of the etching process which has 0.5\um as the minimum line spacing.
+The underlying ONO sandwich, which has been formed in \autoref{sonos_chapter}, which has a spacing of at least a lambda on each side, towards the gate structure, in order to compensate for alignment errors
+will first get its LTO densified during the gate oxide formation phase, and will afterwards experience an alignment with the gate structure during dry etching and its over etching phase.
+
\newpage
\subsection{Gate oxide formation}\label{step_growing_gate_oxide}
diff --git a/process_steps/process_hightech/process_hightech_interconnect.tex b/process_steps/process_hightech/process_hightech_interconnect.tex
index c4ee38e0f430708dd17288a1eafe69a52d25d326..b2bc9a4b0d03e1e11d44c27a83402b58b1a5d522 100644
--- a/process_steps/process_hightech/process_hightech_interconnect.tex
+++ b/process_steps/process_hightech/process_hightech_interconnect.tex
@@ -4,7 +4,7 @@ Now that we've built all the devices, we've got to put wires on them in order to
\begin{figure}[H]
\centering
- \begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
+ \begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossAndTopSectionBig, every node/.style={transform shape}]
\input{tikz_process_steps/glass.a.tex}
\end{tikzpicture}
\caption{Interconnect geometry target}
@@ -13,7 +13,10 @@ Now that we've built all the devices, we've got to put wires on them in order to
From here on it's basically just always the same game:
\begin{enumerate}
- \item Deposit roughly 150nm LTO/PSG
+ \item Deposit roughly 100nm LTO
+ \item Deposit 100nm nitride for CMP end stop
+ \item Deposit roughly 1\um LTO
+ \item CMP away 600nm oxide (regulated by CMP end stop)
\item Etch vias
\item Sputter metal
\item Etch wires
@@ -26,7 +29,7 @@ We have the holes where we sputter the metal into.
All the oxide holes which are \autoref{chapter_contact}, \autoref{chapter_via1}, \autoref{chapter_via2} and \autoref{chapter_glass}, are basically the same,
except that the glass layer is the top oxide opening and doesn't get any more metal sputtered on it.
-We deposit 150nm LTO/PSG and etch holes into it, in order to contact through to the lower layer.
+We deposit 150nm LTO and etch holes into it, in order to contact through to the lower layer.
For the first metal layer (\autoref{chapter_metal1}), the etch stop is silicide and we have to sputter Nickel, as a diffusion barrier, before we sputter any Aluminum,
because the $Ti Si_2$ would react with the Aluminum to an high resistivity material.
diff --git a/process_steps/process_hightech/process_hightech_overview.tex b/process_steps/process_hightech/process_hightech_overview.tex
index 9e5aee43988a687d84df84587bccedaba7fa6c55..446c8e6f740dee46ea90b3541262db5fdd7d46dc 100644
--- a/process_steps/process_hightech/process_hightech_overview.tex
+++ b/process_steps/process_hightech/process_hightech_overview.tex
@@ -1,3 +1,5 @@
+\label{process_hightech_overview}
+
\tikzstyle{block} = [rectangle, draw, fill=blue!20, text width=3cm, text centered, rounded corners, minimum height=1.5cm]
\tikzstyle{line} = [draw, very thick, color=black!50, -latex']
diff --git a/process_steps/process_hightech/process_hightech_steps.pdf b/process_steps/process_hightech/process_hightech_steps.pdf
index 46deb592202d35272ae3779e2c50b10738e9d56f..3b95b749b861b7d98d92d7fda52dfc37ba8509fb 100644
Binary files a/process_steps/process_hightech/process_hightech_steps.pdf and b/process_steps/process_hightech/process_hightech_steps.pdf differ
diff --git a/process_steps/process_hightech/process_hightech_steps.tex b/process_steps/process_hightech/process_hightech_steps.tex
index ca74789e821c65bed71751cf8581b3c465ed7c52..313f20124965089a31983d72494fef0230249d8b 100644
--- a/process_steps/process_hightech/process_hightech_steps.tex
+++ b/process_steps/process_hightech/process_hightech_steps.tex
@@ -76,7 +76,8 @@
\tableofcontents
\newpage
\maketitle
-\input{process_hightech_overview.tex}\label{process_hightech_overview}
+
+\input{process_hightech_overview.tex}
\newpage
\input{process_hightech_shallow_trench_isolation.tex}
\newpage
diff --git a/process_steps/process_hightech/tikz_process_steps/contsts.tex b/process_steps/process_hightech/tikz_process_steps/contsts.tex
index 7de9a84f11e38238bf2dca0abd0777e22244c30a..a2488f893bf631c5babafce08b0134f844816281 100644
--- a/process_steps/process_hightech/tikz_process_steps/contsts.tex
+++ b/process_steps/process_hightech/tikz_process_steps/contsts.tex
@@ -1,5 +1,5 @@
\def\trenchBottom{4.0}
-\def\STIIslandSurface{\trenchBottom+4.0}
+\def\STIIslandSurface{\trenchBottom+2.0}
\def\gateoxidetop{\STIIslandSurface+0.4}
\def\polytop{\gateoxidetop+1.0}
diff --git a/process_steps/process_hightech/tikz_process_steps/sti.resist_removal.b.tex b/process_steps/process_hightech/tikz_process_steps/sti.resist_removal.b.tex
deleted file mode 100644
index d22395adf1503bae0aae1caa83ac90bbdae8a808..0000000000000000000000000000000000000000
--- a/process_steps/process_hightech/tikz_process_steps/sti.resist_removal.b.tex
+++ /dev/null
@@ -1,10 +0,0 @@
-% substrate
-\fill[substrate] (0,0) rectangle (55,\trenchBottom);
-\node at (2,0.5) {Silicon substrate};
-
-% normal wells
-\fill[substrate] (1.25,\trenchBottom) rectangle (8.25,\STIIslandSurface);
-\fill[substrate] (9.75,\trenchBottom) rectangle (16.75,\STIIslandSurface);
-\fill[substrate] (18.25,\trenchBottom) rectangle (25.25,\STIIslandSurface);
-\fill[substrate] (26.75,\trenchBottom) rectangle (33.75,\STIIslandSurface);
-\fill[substrate] (35.25,\trenchBottom) rectangle (42.25,\STIIslandSurface);
diff --git a/process_steps/process_hightech/tikz_process_steps/tripple_well.layout.tex b/process_steps/process_hightech/tikz_process_steps/tripple_well.layout.tex
index f8fd5aab70eb507f108d35da865709593b74a52d..618d7fd2924055e945da9f356112f27bae75c94f 100644
--- a/process_steps/process_hightech/tikz_process_steps/tripple_well.layout.tex
+++ b/process_steps/process_hightech/tikz_process_steps/tripple_well.layout.tex
@@ -13,4 +13,10 @@
\fill[nbase,opacity=\OpacityLayout] (28.75,3.00) rectangle (31.75,5.25);
\fill[nwell,opacity=\OpacityLayout] (35.25,1.00) rectangle (42.25,7.25);
-\fill[pbase,opacity=\OpacityLayout] (35.75,2.00) rectangle (41.75,6.25);
+
+\fill[pbase,opacity=\OpacityLayout] (35.50,2.0) rectangle (36.60,6.25);
+\fill[pbase,opacity=\OpacityLayout] (35.50,5.0) rectangle (42.00,6.25);
+\fill[pbase,opacity=\OpacityLayout] (40.90,2.0) rectangle (42.00,6.25);
+
+\fill[pbase,opacity=\OpacityLayout] (38.20,2.0) rectangle (39.30,4.00);
+