diff --git a/process_steps/process_hightech/process_hightech_interconnect.tex b/process_steps/process_hightech/process_hightech_interconnect.tex
index da5e6d07258bc46ef4e163db94d874634f508d69..31ec03f5908089df3a82a38a1c76ed48b856f7f6 100644
--- a/process_steps/process_hightech/process_hightech_interconnect.tex
+++ b/process_steps/process_hightech/process_hightech_interconnect.tex
@@ -23,12 +23,13 @@ From here on it's basically just always the same game:
\item Go to 1
\end{enumerate}
-As can be seen in \autoref{inteconnect_cross_section}
+As can be seen in \autoref{inteconnect_cross_section}, we have the holes where we sputter the metal into.
-We have the holes where we sputter the metal into.
All the oxide holes which are \autoref{chapter_contact}, \autoref{chapter_via1}, \autoref{chapter_via2} and \autoref{chapter_glass}, are basically the same,
except that the glass layer is the top oxide opening and doesn't get any more metal sputtered on it.
+An example of the general flow can be seen in \autoref{chapter_silicide_and_cmp} where it already has been performed for the interface area between back end and front end process.
+
We deposit 150nm LTO and etch holes into it, in order to contact through to the lower layer.
For the first metal layer (\autoref{chapter_metal1}), the etch stop is silicide and we have to sputter Nickel, as a diffusion barrier, before we sputter any Aluminum,
diff --git a/process_steps/process_hightech/process_hightech_shallow_trench_isolation.tex b/process_steps/process_hightech/process_hightech_shallow_trench_isolation.tex
index 316ff71dff0511e17fb6868a9bbfb246c049eb62..7abcf31e8822ba0971209e2e32179948d9a82fc1 100644
--- a/process_steps/process_hightech/process_hightech_shallow_trench_isolation.tex
+++ b/process_steps/process_hightech/process_hightech_shallow_trench_isolation.tex
@@ -53,7 +53,7 @@ On top of this pad oxide, a layer of around 100nm of nitride is being deposited,
\subsection{Silicon etching}\label{sti_trench_etch}
-The trench depth has to be at least 3.5 microns and less than 4 microns deep, in order to have a sufficiently good isolation for preventing latchup effects and at the same time still good enough ESD diode behaviour.
+The trench depth has to be at least 2 microns and less than 4 microns deep, in order to have a sufficiently good isolation for preventing latchup effects and at the same time still good enough ESD diode behaviour.
\begin{figure}[H]
\centering
@@ -69,9 +69,9 @@ The trench depth has to be at least 3.5 microns and less than 4 microns deep, in
After patterning the STI layout the resist is being hard baked and the nitride+pad oxide is being etched, using plasma etching for nitride+oxide.
-After etching the nitride and oxide we use a DRIE etcher and set the number of cycles in a way that it results in around 3.5 microns trench depth.
+After etching the nitride and oxide we use a DRIE etcher and set the number of cycles in a way that it results in around 2 microns trench depth.
-Adding to the over etch from the previous etch step, this will result in a depth a little bit deeper than 3.5 microns.
+Adding to the over etch from the previous etch step, this will result in a depth a little bit deeper than 2 microns.
\newpage
@@ -109,9 +109,9 @@ Now we fill up the trenches we've etched before with LTO for further planarizati
\caption{Oxide deposition}
\end{figure}
-The easiest method is to put the wafer into a CVD furnace in order to deposit around 3.5 microns of LTO.
+The easiest method is to put the wafer into a CVD furnace in order to deposit around 2 microns of LTO.
-Better uniformity of the LTO film can be achieved by getting the boat out after every deposited micron, rotating it 90 degrees and putting it back in for another deposition round.
+Better uniformity of the LTO film can be achieved by getting the boat out after every deposited 500nm, rotating it 90 degrees and putting it back in for another deposition round.
Also remember to measure the thickness of the deposited LTO under a spectroscope, in order to calculate the approximate CMP time!
@@ -137,12 +137,11 @@ Now the LTO needs to be planarized until a sufficiently low height differential
\caption{After CMP}
\end{figure}
-A CMP is performed, based on a rough time calculation, based on the thickness measurement from \autoref{sti_lto_deposition}, until a height differential below 200nm is being reached.
+A CMP is performed, based on a rough time calculation, based on the thickness measurement from \autoref{sti_lto_deposition}, until a height differential below 200nm is being reached, which can be determined by using a surface profiler.
If available the slurry "SRS-985" should be used because it can significantly increase the yield by reducing the dishing as a study has found\footnote{\url{https://download.libresilicon.com/papers/10.1.1.567.8814.pdf}}.
-After the planarization the wafer needs to be cleaned in hot ammonia and with RCA solution and wafers should kept wet in DI water after CMPing and should not dry out before being cleaned, because this would make particles
-get stuck in the oxide permanently and will destroy the sample.
+After the planarization the wafer needs to be cleaned in hot ammonia and with RCA solution and wafers should kept wet in DI water after CMPing and should not dry out before being cleaned, because this would make particles get stuck in the oxide permanently and will destroy the sample.
After cleaning the LTO has to be annealed in order to increase the etching time when removing the pad oxide: The sample is being put into a furnace for 30 minutes at 850\degreesC in an inert atmosphere ($N_2$/$Ar$).
diff --git a/process_steps/process_hightech/process_hightech_silicification.tex b/process_steps/process_hightech/process_hightech_silicification.tex
index 9098852df3663a33f4b4571e0f197e81980b0eed..bf32ef505f4d58294dfaa1ba38e171a13f0343cf 100644
--- a/process_steps/process_hightech/process_hightech_silicification.tex
+++ b/process_steps/process_hightech/process_hightech_silicification.tex
@@ -70,7 +70,7 @@ Thit means the etching process only "sees" the sidewall as a "thicker layer" and
\caption{Anisotropic etching}
\end{figure}
-After that we will have our desired spacer geometry forming as well as any potentially resist covered area (if silicide block is being used) with sharp etches.
+After that we will have our desired spacer geometry forming as well as any potentially resist covered area from the silicide block mask patterns, which will allow us to control in which areas we reduce the sheet resistance in which we don't.
\newpage
@@ -92,8 +92,6 @@ We deposit a layer of titanium with a thickness of around 30nm which will then b
The titanium can either be applied by sputtering or by chemical deposition.
-\newpage
-
\subsection{Silicide formation}
The deposited Ti film reacts with the exposed silicon areas such as the source/drain area and polysilicon gate electrodes during RTP (Rapid Thermal Processing) at 800\degreesC in Argon ambient for 30 seconds.
@@ -114,7 +112,9 @@ In this annealing step the $Ti Si_2$ is formed.
The resulting $Ti Si_2$ film will be around 77nm in tickness with around 20nm unreacted titanium left on top.
-A color change can be observed of the titanium on top of the oxide.
+A color change into a slightly brownish color from originally silver metallic can be observed of the titanium on top of the oxide.
+
+\newpage
\subsection{Metal removal}
@@ -133,8 +133,7 @@ The unreacted titanium film on the dielectric layer such as $SiO_2$ or $SiN$ is
\end{figure}
After 2-3 minutes in APM, at room temperature, with a bit mechanical help, all the unreacted Titanium should be gone and the oxide should become visible again.
-
-\newpage
+Under \textbf{no circumstance} use a solvent containing HF, since $Ti Si_2$ dissolves in HF or any other Fluoride containing solutions.
\subsection{CMP}\label{chapter_silicide_and_cmp}
@@ -146,14 +145,10 @@ our devices will not be damaged during the planarization phase in order to conta
\begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
\input{tikz_process_steps/silicification.cmp_stop.a.tex}
\end{tikzpicture}
- \drawStepArrow{CMP endstop}
+ \drawStepArrow{LTO+CMP}
\begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
\input{tikz_process_steps/silicification.cmp_stop.b.tex}
\end{tikzpicture}
- \drawStepArrow{CMP}
- \begin{tikzpicture}[node distance = 3cm, auto, thick,scale=\CrossSectionOnly, every node/.style={transform shape}]
- \input{tikz_process_steps/silicification.cmp_stop.c.tex}
- \end{tikzpicture}
\caption{CMP, contact preparation}
\end{figure}
@@ -163,5 +158,8 @@ Then we deposit 1\um LTO and CMP away the height differential of the active devi
LTO was chosen because the silicide becomes unstable in the thermal ranges where phosphorus silicate glass becomes viscous enough
for evening out the height differential by evening out by seeking its level during annealing.
-A thickness of 1\um of the LTO will make it more likely, that the dishing effect of the CMP pad causes devices to get damaged
+A thickness of 1\um of the LTO will make it less likely, that the dishing effect of the CMP pad causes devices to get damaged
through an over consumption of the nitride hard mask.
+
+The best approach for depositing this LTO layer is to split the deposition into 4 steps at each 250nm and rotating the sample
+90 degrees between the steps in order to improve uniformity of the LTO layer.
diff --git a/process_steps/process_hightech/process_hightech_steps.pdf b/process_steps/process_hightech/process_hightech_steps.pdf
index 0e2d6e5f9ea9cff9450c3562aab89cf72253153d..0a9aadc491cf01f9356121cf8a3924782814620b 100644
Binary files a/process_steps/process_hightech/process_hightech_steps.pdf and b/process_steps/process_hightech/process_hightech_steps.pdf differ