From b654c46ebb91aae450a9c5a7b1270e8830d7110f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <leviathan@libresilicon.com>
Date: Wed, 3 Jul 2024 14:36:11 +0100
Subject: [PATCH] We need SystemVerilog features
---
src/rtl/{network_controller.v => network_controller.sv} | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
rename src/rtl/{network_controller.v => network_controller.sv} (95%)
diff --git a/src/rtl/network_controller.v b/src/rtl/network_controller.sv
similarity index 95%
rename from src/rtl/network_controller.v
rename to src/rtl/network_controller.sv
index a2e3810..bb88ef3 100644
--- a/src/rtl/network_controller.v
+++ b/src/rtl/network_controller.sv
@@ -154,9 +154,11 @@ module network_controller #(
reg read_done;
// Map to bytes:
- for(gv=0; gv<4; gv++) begin
- assign bytes_i[gv] = mem_data_i[(gv+1)*8-1:gv*8];
- end
+ generate
+ for(gv=0; gv<4; gv=gv+1) begin : map_mem_bytes
+ assign bytes_i[gv] = mem_data_i[(gv+1)*8-1:gv*8];
+ end
+ endgenerate
assign wr_enable = &mem_wstrb;
--
GitLab