From 9040a27ed45684f30cbc5de5eab7898f4e6c6c6a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <leviathan@libresilicon.com>
Date: Sun, 30 Jun 2024 09:51:57 +0100
Subject: [PATCH] Add threading

---
 .gitlab-ci.yml | 2 +-
 Makefile       | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 9a7b6d7..c27975d 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -31,7 +31,7 @@ train_test:
   stage: build
   script:
   - mkdir -p result
-  - make
+  - make CICD_VERILATOR_CFLAGS="--threads 8 --threads-dpi all"
   - ./testbench_ecp5_minifpga.bin &
   - sleep 1s && python3 src/py/tty3.py
   artifacts:
diff --git a/Makefile b/Makefile
index 3ebad1a..56bdf1f 100644
--- a/Makefile
+++ b/Makefile
@@ -8,6 +8,8 @@ NETWORK_PARAMS = \
 
 TARGET_BOARD?=ecp5_minifpga
 
+CICD_VERILATOR_CFLAGS?=
+
 BENCHES=
 
 VERILATOR_DIR?=/usr/share/verilator/include
@@ -67,7 +69,7 @@ testbench_%.bin: obj_dir/V%__ALL.a src/cpptb/%.cpp src/cpptb/params.h
 	rm -rf obj_dir
 
 obj_dir/V%__ALL.a: src/rtl/%.v src/rtl/params.vh
-	$(VERILATOR) --top-module $* -cc src/rtl/$*.v -Isrc/rtl
+	$(VERILATOR) $(CICD_VERILATOR_CFLAGS) --top-module $* -cc src/rtl/$*.v -Isrc/rtl
 	make -C obj_dir -f V$*.mk
 
 result/soc.json: result/firmware.hex src/rtl/params.vh result
-- 
GitLab