From 287f1cf4cf385ddab691856a6b32f171665e1334 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <leviathan@libresilicon.com>
Date: Wed, 3 Jul 2024 14:13:38 +0100
Subject: [PATCH] We need SystemVerilog features

---
 src/rtl/{neuron.v => neuron.sv} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename src/rtl/{neuron.v => neuron.sv} (100%)

diff --git a/src/rtl/neuron.v b/src/rtl/neuron.sv
similarity index 100%
rename from src/rtl/neuron.v
rename to src/rtl/neuron.sv
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