From dfb42d07651518a14a123a8aff819d3edb6f4bd0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= <leviathan@libresilicon.com>
Date: Wed, 1 Mar 2023 23:11:19 +0000
Subject: [PATCH] Resolve design rule error
---
technologies/gf180.tech.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/technologies/gf180.tech.py b/technologies/gf180.tech.py
index b14726a..e054dbd 100644
--- a/technologies/gf180.tech.py
+++ b/technologies/gf180.tech.py
@@ -333,7 +333,7 @@ minimum_width = {
l_metal2: 280*nm, # Mn.1
l_metal3: 280*nm, # Mn.1
l_metal4: 280*nm, # Mn.1
- l_metal5: 440*nm, # Mn.1
+ l_metal5: 460*nm, # Mn.1
l_nwell: 860*nm, # NW.1a
l_pwell: 740*nm, # LPW.1
l_nplus: 400*nm # NP.1
--
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